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parallel nor flash embedded memory jr28f032m29ewxx; pz28f032m29ewxx; js28f064m29ewxx pc28f064m29ewxx; jr28f064m29ewxx; pz28f064m29ewxx js28f128m29ewxx; pc28f128m29ewxx; rc28f128m29ewxx features ? supply voltage C v cc = 2.7C3.6v (program, erase, read) C v ccq = 1.65C3.6v (i/o buffers) ? asynchronous random or page read C page size: 8 words or 16 bytes C page access: 25ns C random access: 60ns (bga); 70ns (tsop) ? buffer program: 256-word max program buffer ? program time C 0.56s per byte (1.8 mb/s typ when using 256- word buffer size in buffer program without v pph ) C 0.31s per byte (3.2 mb/s typ when using 256- word buffer size in buffer program with v pph ) ? memory organization C 32mb: 64 main blocks, 64kb each, or eight 8kb boot blocks (top or bottom) and 63 main blocks, 64kb each C 64mb: 128 main blocks, 64kb each, or eight 8kb boot blocks (top or bottom) and 127 main blocks, 64 kb each C 128mb: 128 main blocks, 128kb each ? program/erase controller C embedded byte/word program algorithms ? program/erase suspend and resume capability C read operation on any block during a pro- gram suspend operation C read or program operation on one block dur- ing an erase suspend operation on another block ? blank check operation to verify an erased block ? unlock bypass, block erase, chip erase, and write to buffer capability C fast buffered/batch programming C fast block and chip erase ? v pp /wp# pin protection C v pph voltage on v pp to accelerate programming performance C protects highest/lowest block (h/l uniform) or top/bottom two blocks (t/b boot) ? software protection C volatile protection C nonvolatile protection C password protection C password access ? extended memory block C 128-word (256-byte) block for permanent secure identification C program or lock implemented at the factory or by the customer ? low-power consumption: standby mode ? jesd47h-compliant C 100,000 minimum erase cycles per block C data retention: 20 years (typ) ? 65nm single-bit cell process technology ? packages (jedec-standard) C 56-pin tsop (128mb, 64mb) C 48-pin tsop (64mb, 32mb) C 64-ball fbga (128mb, 64mb) C 48-ball bga (64mb, 32mb) ? green packages available C rohs-compliant C halogen-free ? operating temperature C ambient: C40c to +85c 32mb, 64mb, 128mb: 3v embedded parallel nor flash features pdf: 09005aef84dc44a7 m29ew_32mb-128mb.pdf - rev. b 11/12 en 1 micron technology, inc. reserves the right to change products or specifications without notice. ? 2012 micron technology, inc. all rights reserved. products and specifications discussed herein are subject to change by micron without notice.
part numbering information this product is available with the prelocked extended memory block. devices are shipped from the factory with memory content bits erased to 1. for a list of available options, such as packages or high/low protection, or for further information, contact your micron sales representative. table 1: part number information part number category category details package js = 56-pin tsop, 14mm x 20mm, lead-free, halogen-free, rohs-compliant pc = 64-ball fortified bga, 11mm x 13mm, lead-free, halogen-free, rohs-compliant rc = 64-ball fortified bga, 11mm x 13mm, leaded jr = 48-pin tsop, 12mm x 20mm, lead-free, halogen-free, rohs-compliant pz = 48-ball bga, 6mm x 8mm, lead-free, halogen-free, rohs-compliant product designator 28f = parallel nor interface density 128 = 128mb 064 = 64mb 032 = 32mb device type m29ew = embedded flash memory (3v core, page read) device function h = highest block protected by v pp /wp#; uniform block l = lowest block protected by v pp /wp#; uniform block b = bottom boot; bottom two blocks protected by v pp /wp# t = top boot; top two blocks protected by v pp /wp# features a/b/f/x or an asterisk (*) = combination of features, including packing media, security features, and specific customer request information valid m29ew part number combinations table 2: standard part numbers by density, medium, and package density medium package js pc rc jr pz 32mb tray C C C jr28f032m29ewha pz28f032m29ewha jr28f032m29ewla pz28f032m29ewla jr28f032m29ewba pz28f032m29ewba jr28f032m29ewta pz28f032m29ewta tape and reel C C C jr28f032m29ewbb pz28f032m29ewbb jr28f032m29ewtb 32mb, 64mb, 128mb: 3v embedded parallel nor flash features pdf: 09005aef84dc44a7 m29ew_32mb-128mb.pdf - rev. b 11/12 en 2 micron technology, inc. reserves the right to change products or specifications without notice. ? 2012 micron technology, inc. all rights reserved.
table 2: standard part numbers by density, medium, and package (continued) density medium package js pc rc jr pz 64mb tray js28f064m29ewha pc28f064m29ewha C jr28f064m29ewha pz28f064m29ewha js28f064m29ewla pc28f064m29ewla jr28f064m29ewla pz28f064m29ewla js28f064m29ewba pc28f064m29ewba jr28f064m29ewba pz28f064m29ewba js28f064m29ewta pc28f064m29ewta jr28f064m29ewta pz28f064m29ewta tape and reel js28f064m29ewlb C C jr28f064m29ewhb pz28f064m29ewbb jr28f064m29ewlb jr28f064m29ewtb 128mb tray js28f128m29ewhf PC28F128M29EWHF rc28f128m29ewhf C C js28f128m29ewla pc28f128m29ewla rc28f128m29ewla tape and reel C C C C C table 3: part numbers with security features by density, medium, and package density medium package pc pz 64mb tray pc28f064m29ewhx pz28f064m29ewhx pc28f064m29ewlx pz28f064m29ewlx pc28f064m29ewbx pz28f064m29ewbx pc28f064m29ewtx pz28f064m29ewtx tape and reel pc28f064m29ewty C 128mb tray pc28f128m29ewhx C pc28f128m29ewlx tape and reel C C note: 1. this data sheet covers only standard parts. for security parts, contact your local micron sales representative. 32mb, 64mb, 128mb: 3v embedded parallel nor flash features pdf: 09005aef84dc44a7 m29ew_32mb-128mb.pdf - rev. b 11/12 en 3 micron technology, inc. reserves the right to change products or specifications without notice. ? 2012 micron technology, inc. all rights reserved.
contents general description ......................................................................................................................................... 8 signal assignments ........................................................................................................................................... 9 signal descriptions ......................................................................................................................................... 13 memory organization .................................................................................................................................... 14 memory configuration ............................................................................................................................... 14 memory map C 32mb ................................................................................................................................. 15 memory map C 64mb ................................................................................................................................. 17 memory map C 128mb ................................................................................................................................ 19 bus operations ............................................................................................................................................... 20 read .......................................................................................................................................................... 20 write .......................................................................................................................................................... 20 standby ..................................................................................................................................................... 20 output disable ........................................................................................................................................... 21 reset .......................................................................................................................................................... 21 registers ........................................................................................................................................................ 22 status register ............................................................................................................................................ 22 lock register .............................................................................................................................................. 27 standard command definitions C address-data cycles .................................................................................... 30 read and auto select operations .............................................................................................................. 33 read/reset command ............................................................................................................................ 33 read cfi command .................................................................................................................................. 33 auto select command ........................................................................................................................... 33 bypass operations .......................................................................................................................................... 35 unlock bypass command ...................................................................................................................... 35 unlock bypass reset command ............................................................................................................ 36 program operations ....................................................................................................................................... 36 program command ................................................................................................................................ 36 unlock bypass program command ..................................................................................................... 37 double byte/word program command ............................................................................................. 37 quadruple byte/word program command ...................................................................................... 37 octuple byte program command ....................................................................................................... 38 write to buffer program command .................................................................................................. 38 unlock bypass write to buffer program command ....................................................................... 40 enhanced write to buffer program command ............................................................................... 41 unlock bypass enhanced write to buffer program command ................................................... 41 write to buffer program confirm command .................................................................................. 42 enhanced write to buffer program confirm command .............................................................. 42 buffered program abort and reset command ................................................................................ 42 program suspend command ................................................................................................................ 42 program resume command .................................................................................................................. 43 erase operations ............................................................................................................................................ 43 chip erase command .............................................................................................................................. 43 unlock bypass chip erase command ................................................................................................... 43 block erase command ........................................................................................................................... 44 unlock bypass block erase command ................................................................................................ 44 erase suspend command ....................................................................................................................... 44 erase resume command ........................................................................................................................ 45 blank check operation .............................................................................................................................. 45 blank check commands ........................................................................................................................ 45 block protection command definitions C address-data cycles ........................................................................ 47 32mb, 64mb, 128mb: 3v embedded parallel nor flash features pdf: 09005aef84dc44a7 m29ew_32mb-128mb.pdf - rev. b 11/12 en 4 micron technology, inc. reserves the right to change products or specifications without notice. ? 2012 micron technology, inc. all rights reserved.
protection operations .................................................................................................................................... 50 lock register commands ...................................................................................................................... 50 password protection commands ....................................................................................................... 50 nonvolatile protection commands .................................................................................................. 50 nonvolatile protection bit lock bit commands ............................................................................ 53 volatile protection commands .......................................................................................................... 53 extended memory block commands .................................................................................................. 53 exit protection command .................................................................................................................... 54 device protection ........................................................................................................................................... 55 hardware protection .................................................................................................................................. 55 software protection .................................................................................................................................... 55 volatile protection mode ............................................................................................................................. 56 nonvolatile protection mode ...................................................................................................................... 56 password protection mode .......................................................................................................................... 57 password access ......................................................................................................................................... 57 common flash interface ................................................................................................................................ 59 power-up and reset characteristics ................................................................................................................ 64 absolute ratings and operating conditions ..................................................................................................... 66 dc characteristics .......................................................................................................................................... 68 read ac characteristics .................................................................................................................................. 70 write ac characteristics ................................................................................................................................. 73 accelerated program, data polling/toggle ac characteristics ........................................................................... 80 electrical specifications C program/erase characteristics ................................................................................. 82 package dimensions ....................................................................................................................................... 83 revision history ............................................................................................................................................. 87 rev. b C 11/12 ............................................................................................................................................. 87 rev. a C 08/12 ............................................................................................................................................. 87 32mb, 64mb, 128mb: 3v embedded parallel nor flash features pdf: 09005aef84dc44a7 m29ew_32mb-128mb.pdf - rev. b 11/12 en 5 micron technology, inc. reserves the right to change products or specifications without notice. ? 2012 micron technology, inc. all rights reserved.
list of figures figure 1: logic diagram ................................................................................................................................... 8 figure 2: 56-pin tsop (top view) .................................................................................................................... 9 figure 3: 48-pin tsop (top view) .................................................................................................................. 10 figure 4: 48-ball bga (top and bottom views) ............................................................................................... 11 figure 5: 64-ball fortified bga (top and bottom views) .................................................................................. 12 figure 6: data polling flowchart .................................................................................................................... 24 figure 7: toggle bit flowchart ........................................................................................................................ 25 figure 8: status register polling flowchart ..................................................................................................... 26 figure 9: lock register program flowchart ..................................................................................................... 28 figure 10: boundary condition of program buffer size .................................................................................... 39 figure 11: write to buffer program flowchart ...................................................................................... 40 figure 12: program/erase nonvolatile protection bit algorithm ...................................................................... 52 figure 13: software protection scheme .......................................................................................................... 57 figure 14: power-up timing .......................................................................................................................... 64 figure 15: reset ac timing C no program/erase operation in progress ...................................................... 65 figure 16: reset ac timing during program/erase operation .................................................................... 65 figure 17: ac measurement load circuit ....................................................................................................... 67 figure 18: ac measurement i/o waveform ..................................................................................................... 67 figure 19: random read ac timing (8-bit mode) ........................................................................................... 71 figure 20: random read ac timing (16-bit mode) ......................................................................................... 71 figure 21: byte# transition read ac timing .................................................................................................. 72 figure 22: page read ac timing (16-bit mode) ............................................................................................... 72 figure 23: we#-controlled program ac timing (8-bit mode) .......................................................................... 74 figure 24: we#-controlled program ac timing (16-bit mode) ......................................................................... 75 figure 25: ce#-controlled program ac timing (8-bit mode) ........................................................................... 77 figure 26: ce#-controlled program ac timing (16-bit mode) ......................................................................... 78 figure 27: chip/block erase ac timing (8-bit mode) ...................................................................................... 79 figure 28: accelerated program ac timing ..................................................................................................... 80 figure 29: data polling ac timing .................................................................................................................. 80 figure 30: toggle/alternative toggle bit polling ac timing (8-bit mode) .......................................................... 81 figure 31: 56-pin tsop C 14mm x 20mm ........................................................................................................ 83 figure 32: 48-pin tsop C 12mm x 20mm ........................................................................................................ 84 figure 33: 48-ball bga C 6mm x 8mm ............................................................................................................. 85 figure 34: 64-ball fortified bga C 11mm x 13mm ........................................................................................... 86 32mb, 64mb, 128mb: 3v embedded parallel nor flash features pdf: 09005aef84dc44a7 m29ew_32mb-128mb.pdf - rev. b 11/12 en 6 micron technology, inc. reserves the right to change products or specifications without notice. ? 2012 micron technology, inc. all rights reserved.
list of tables table 1: part number information ................................................................................................................... 2 table 2: standard part numbers by density, medium, and package ................................................................... 2 table 3: part numbers with security features by density, medium, and package ................................................ 3 table 4: signal descriptions ........................................................................................................................... 13 table 5: 32mb memory map C x8 top and bottom boot [70:0] ......................................................................... 15 table 6: 32mb memory map C x16 top and bottom boot [70:0] ........................................................................ 15 table 7: 32mb memory map C x8/x16 uniform blocks [63:0] ............................................................................ 16 table 8: 64mb memory map C x8 top and bottom boot [134:0] ........................................................................ 17 table 9: 64mb memory map C x16 top and bottom boot [134:0] ...................................................................... 17 table 10: 64mb memory map C x8/x16 uniform blocks [127:0] ........................................................................ 18 table 11: 128mb memory map C x8/x16 uniform blocks [127:0] ...................................................................... 19 table 12: bus operations ............................................................................................................................... 20 table 13: status register bit definitions ......................................................................................................... 22 table 14: operations and corresponding bit settings ...................................................................................... 23 table 15: lock register bit definitions ............................................................................................................ 27 table 16: block protection status ................................................................................................................... 27 table 17: standard command definitions C address-data cycles, 8-bit and 16-bit ........................................... 30 table 18: read electronic signature ............................................................................................................... 34 table 19: block protection ............................................................................................................................. 35 table 20: block protection command definitions C address-data cycles, 8-bit and 16-bit ................................ 47 table 21: extended memory block address and data ...................................................................................... 53 table 22: v pp /wp# functions ......................................................................................................................... 55 table 23: query structure overview ............................................................................................................... 59 table 24: cfi query identification string ........................................................................................................ 59 table 25: cfi query system interface information .......................................................................................... 60 table 26: device geometry definition ............................................................................................................ 60 table 27: erase block region information ....................................................................................................... 61 table 28: primary algorithm-specific extended query table ........................................................................... 62 table 29: power-up specifications ................................................................................................................. 64 table 30: reset ac specifications ................................................................................................................... 65 table 31: absolute maximum/minimum ratings ............................................................................................ 66 table 32: operating conditions ...................................................................................................................... 66 table 33: input/output capacitance .............................................................................................................. 67 table 34: dc current characteristics .............................................................................................................. 68 table 35: dc voltage characteristics .............................................................................................................. 69 table 36: read ac characteristics .................................................................................................................. 70 table 37: we#-controlled write ac characteristics ......................................................................................... 73 table 38: ce#-controlled write ac characteristics ......................................................................................... 76 table 39: accelerated program and data polling/data toggle ac characteristics .............................................. 80 table 40: program/erase characteristics ........................................................................................................ 82 32mb, 64mb, 128mb: 3v embedded parallel nor flash features pdf: 09005aef84dc44a7 m29ew_32mb-128mb.pdf - rev. b 11/12 en 7 micron technology, inc. reserves the right to change products or specifications without notice. ? 2012 micron technology, inc. all rights reserved.
general description the m29ew is an asynchronous, parallel nor flash memory device manufactured on 65nm single-bit cell (sbc) technology. read, erase, and program operations are performed using a single low-voltage supply. upon power-up, the device defaults to read array mode. the main memory array is divided into uniform blocks that can be erased independent- ly so that valid data can be preserved while old data is purged. program and erase commands are written to the command interface of the memory. an on-chip program/ erase controller simplifies the process of programming or erasing the memory by taking care of all special operations required to update the memory contents. the end of a program or erase operation can be detected and any error condition can be identi- fied. the command set required to control the device is consistent with jedec stand- ards. ce#, oe#, and we# control the bus operation of the device and enable a simple con- nection to most microprocessors, often without additional logic. the m29ew supports asynchronous random read and page read from all blocks of the array. it also features an internal program buffer that improves throughput by program- ming 256 words via one command sequence. the device contains a 128-word extended memory block which overlaps addresses with array block 0. the user can program this additional space and then protect it to permanently secure the contents. the device al- so features different levels of hardware and software protection to secure blocks from unwanted modification. figure 1: logic diagram v cc v ccq a[max:0] we# v pp /wp# dq[14:0] dq15/a-1 v ss 15 ce# oe# rst# byte# ry/by# 32mb, 64mb, 128mb: 3v embedded parallel nor flash general description pdf: 09005aef84dc44a7 m29ew_32mb-128mb.pdf - rev. b 11/12 en 8 micron technology, inc. reserves the right to change products or specifications without notice. ? 2012 micron technology, inc. all rights reserved.
signal assignments figure 2: 56-pin tsop (top view) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 rfu a22 a15 a14 a13 a12 a11 a10 a9 a8 a19 a20 we# rst# a21 v pp /wp# ry/by# a18 a17 a7 a6 a5 a4 a3 a2 a1 rfu rfu rfu rfu a16 byte# v ss dq15/a-1 dq7 dq14 dq6 dq13 dq5 dq12 dq4 v cc dq11 dq3 dq10 dq2 dq9 dq1 dq8 dq0 oe# v ss ce# a0 rfu v ccq notes: 1. a-1 is the least significant address bit in x8 mode. 2. a21 is valid for 64mb and above; otherwise, it is rfu. 3. a22 is valid for 128mb and above; otherwise, it is rfu. 4. rfu = reserved for future use. 32mb, 64mb, 128mb: 3v embedded parallel nor flash signal assignments pdf: 09005aef84dc44a7 m29ew_32mb-128mb.pdf - rev. b 11/12 en 9 micron technology, inc. reserves the right to change products or specifications without notice. ? 2012 micron technology, inc. all rights reserved.
figure 3: 48-pin tsop (top view) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 a15 a14 a13 a12 a11 a10 a9 a8 a19 a20 we# rst# a21 v pp /wp# ry/by# a18 a17 a7 a6 a5 a4 a3 a2 a1 a0 a16 byte# v ss dq15/a-1 dq7 dq14 dq6 dq13 dq5 dq12 dq4 v cc dq11 dq3 dq10 dq2 dq9 dq1 dq8 dq0 oe# ce# v ss notes: 1. a-1 is the least significant address bit in x8 mode. 2. a21 is valid for 64mb and above; otherwise, it is rfu. 3. rfu = reserved for future use. 32mb, 64mb, 128mb: 3v embedded parallel nor flash signal assignments pdf: 09005aef84dc44a7 m29ew_32mb-128mb.pdf - rev. b 11/12 en 10 micron technology, inc. reserves the right to change products or specifications without notice. ? 2012 micron technology, inc. all rights reserved.
figure 4: 48-ball bga (top and bottom views) a b c d e f g h a b c d e f g h 1 a3 a2 a4 a1 a0 ce# oe# 2 a7 a17 a6 a5 d0 d8 d9 d1 v ss 3 ry/by# v pp /wp# a18 a20 d2 d10 d11 d3 3 ry/by# v pp /wp# a18 a20 d2 d10 d11 d3 4 we# rst# a21 a19 d5 d12 v cc d4 4 we# rst# a21 a19 d5 d12 v cc d4 5 a9 a8 a10 a11 d7 d14 d13 d6 5 a9 a8 a10 a11 d7 d14 d13 d6 6 a13 a12 a14 a15 a16 byte# d15/a-1 v ss 6 a13 a12 a14 a15 a16 byte# d15/a-1 v ss 2 a7 a17 a6 a5 d0 d8 d9 d1 1 a3 a4 a2 a1 a0 ce# oe# v ss bga top view C ball side down bga bottom view C ball side up notes: 1. a-1 is the least significant address bit in x8 mode. 2. a21 is valid for 64mb and above; otherwise, it is rfu. 3. rfu = reserved for future use. 32mb, 64mb, 128mb: 3v embedded parallel nor flash signal assignments pdf: 09005aef84dc44a7 m29ew_32mb-128mb.pdf - rev. b 11/12 en 11 micron technology, inc. reserves the right to change products or specifications without notice. ? 2012 micron technology, inc. all rights reserved.
figure 5: 64-ball fortified bga (top and bottom views) a b c d e f g h a b c d e f g h 1 rfu rfu rfu rfu rfu v ccq rfu rfu 2 a3 a4 a2 a1 a0 ce# oe# v ss 3 a7 a17 a6 a5 d0 d8 d9 d1 4 ry/by# v pp /wp# a18 a20 d2 d10 d11 d3 4 ry/by# v pp /wp# a18 a20 d2 d10 d11 d3 5 we# rst# a21 a19 d5 d12 v cc d4 5 we# rst# a21 a19 d5 d12 v cc d4 6 a9 a8 a10 a11 d7 d14 d13 d6 6 a9 a8 a10 a11 d7 d14 d13 d6 7 a13 a12 a14 a15 a16 byte# d15/a-1 v ss 7 a13 a12 a14 a15 a16 byte# d15/a-1 v ss 8 rfu a22 rfu v ccq v ss rfu rfu rfu 8 rfu a22 rfu v ccq v ss rfu rfu rfu 3 a7 a17 a6 a5 d0 d8 d9 d1 2 a3 a4 a2 a1 a0 ce# oe# v ss 1 rfu rfu rfu rfu rfu v ccq rfu rfu fortified bga top view C ball side down fortified bga bottom view C ball side up notes: 1. a-1 is the least significant address bit in x8 mode. 2. a21 is valid for 64mb and above; otherwise, it is rfu. 3. a22 is valid for 128mb and above; otherwise, it is rfu. 4. rfu = reserved for future use. 32mb, 64mb, 128mb: 3v embedded parallel nor flash signal assignments pdf: 09005aef84dc44a7 m29ew_32mb-128mb.pdf - rev. b 11/12 en 12 micron technology, inc. reserves the right to change products or specifications without notice. ? 2012 micron technology, inc. all rights reserved.
signal descriptions the signal description table below is a comprehensive list of signals for this device fami- ly. all signals listed may not be supported on this device. see signal assignments for in- formation specific to this device. table 4: signal descriptions name type description a[max:0] input address: selects the cells in the array to access during read operations. during write oper- ations, they control the commands sent to the command interface of the program/erase con- troller. ce# input chip enable: activates the device, enabling read and write operations to be performed. when ce# is high, the device goes to standby and data outputs are at high-z. oe# input output enable: controls the bus read operation. we# input write enable: controls the bus write operation of the command interface. v pp /wp# input v pp /write protect: provides write protect function and v pph function. these functions protect the lowest or highest block or top two blocks or bottom two blocks, enable the de- vice to enter unlock bypass mode and accelerate program speed, respectively. (refer to hard- ware protection, bypass operations, and program operations for details.) a 0.1 f capacitor should be connected between v pp /wp# and v ss to decouple the current surges from the power supply when v pph is applied. the pcb track widths must be sufficient to carry the currents required during program and erase operation when v pph is applied (see dc characteristics). byte# input byte/word organization select: switches between x8 and x16 bus modes. when byte# is low, the device is in x8 mode; when high, the device is in x16 mode. rst# input reset: applies a hardware reset to the device, which is achieved by holding rst# low for at least t plpx. after rst# goes high, the device is ready for read and write operations (after t phel or t rhel, whichever occurs last). see reset ac specifications for more details. dq[7:0] i/o data i/o: outputs the data stored at the selected address during a read operation. during write operations, they represent the commands sent to the command interface of the inter- nal state machine. dq[14:8] i/o data i/o: outputs the data stored at the selected address during a read operation when byte# is high. when byte# is low, these pins are not used and are high-z. during write operations, these bits are not used. when reading the status register, these bits should be ig- nored. dq15/a-1 i/o data i/o or address input: when the device operates in x16 bus mode, this pin behaves as data i/o, together with dq[14:8]. when the device operates in x8 bus mode, this pin behaves as the least significant bit of the address. except where stated explicitly otherwise, dq15 = data i/o (x16 mode); a-1 = address input (x8 mode). 32mb, 64mb, 128mb: 3v embedded parallel nor flash signal descriptions pdf: 09005aef84dc44a7 m29ew_32mb-128mb.pdf - rev. b 11/12 en 13 micron technology, inc. reserves the right to change products or specifications without notice. ? 2012 micron technology, inc. all rights reserved.
table 4: signal descriptions (continued) name type description ry/by# output ready busy: open-drain output that can be used to identify when the device is performing a program or erase operation. during program or erase operations, ry/by# is low, and is high-z during read mode, auto select mode, and erase suspend mode. after a hard- ware reset, read and write operations cannot begin until ry/by# goes high-z (see reset ac specifications for more details). the use of an open-drain output enables the ry/by# pins from several devices to be connec- ted to a single pull-up resistor to v ccq . a low value will then indicate that one (or more) of the devices is (are) busy. a 10k ohm or bigger resistor is recommended as pull-up resistor to achieve 0.1v v ol . v cc supply supply voltage: provides the power supply for read, program, and erase operations. the command interface is disabled when v cc <= v lko . this prevents write operations from accidentally damaging the data during power-up, power-down, and power surges. if the pro- gram/erase controller is programming or erasing during this time, then the operation aborts and the contents being altered will be invalid. a 0.1 f capacitor should be connected between v cc and v ss to decouple the current surges from the power supply. the pcb track widths must be sufficient to carry the currents required during program and erase operations (see dc characteristics). v ccq supply i/o supply voltage: provides the power supply to the i/o pins and enables all outputs to be powered independently from v cc . v ss supply ground: all v ss pins must be connected to the system ground. rfu C reserved for future use: rfus should be not connected. memory organization memory configuration the 32mb device memory array (x8/x16) is divided into 63 main blocks (64kb each) and 8 top or bottom boot blocks (8kb each). it is also divided into 64 main uniform blocks (64kb each). the 64mb device memory array (x8/x16) is divided into 127 main blocks (64kb each) and 8 top or bottom boot blocks (8kb each). it is also divided into 128 main uniform blocks (64kb each). the 128mb device memory array (x8/x16) is divided into 128 main uniform blocks (128kb each). 32mb, 64mb, 128mb: 3v embedded parallel nor flash memory organization pdf: 09005aef84dc44a7 m29ew_32mb-128mb.pdf - rev. b 11/12 en 14 micron technology, inc. reserves the right to change products or specifications without notice. ? 2012 micron technology, inc. all rights reserved.
memory map C 32mb table 5: 32mb memory map C x8 top and bottom boot [70:0] block block size address range (x8 top boot) block block size address range (x8 bottom boot) start end start end 70 8kb 003f e000 003f ffff 70 64kb 003f 0000 003f ffff 69 003f c000 003f dfff 69 003e 0000 003e ffff 68 003f a000 003f bfff 68 003d 0000 003d ffff 67 003f 8000 003f 9fff ? ? ? ? 66 003f 6000 003f 7fff 8 64kb 0001 0000 0001 ffff 65 003f 4000 003f 5fff 7 8kb 0000 e000 0000 ffff 64 003f 2000 003f 3fff 6 0000 c000 0000 dfff 63 003f 0000 003f 1fff 5 0000 a000 0000 bfff 62 64kb 003e 0000 003e ffff 4 0000 8000 0000 9fff ? ? ? ? 3 0000 6000 0000 7fff 2 64kb 0002 0000 0002 ffff 2 0000 4000 0000 5fff 1 0001 0000 0001 ffff 1 0000 2000 0000 3fff 0 0000 0000 0000 ffff 0 0000 0000 0000 1fff table 6: 32mb memory map C x16 top and bottom boot [70:0] block block size address range (x16 top boot) block block size address range (x16 bottom boot) start end start end 70 4kw 001f f000 001f ffff 70 32kw 001f 8000 001f ffff 69 001f e000 001f efff 69 001f 0000 001f 7fff 68 001f d000 001f dfff 68 001e 8000 001e ffff 67 001f c000 001f cfff ? ? ? ? 66 001f b000 001f bfff 8 32kw 0000 8000 0000 ffff 65 001f a000 001f afff 7 4kw 0000 7000 0000 7fff 64 001f 9000 001f 9fff 6 0000 6000 0000 6fff 63 001f 8000 001f 8fff 5 0000 5000 0000 5fff 62 32kw 001f 0000 001f 7fff 4 0000 4000 0000 4fff ? ? ? ? 3 0000 3000 0000 3fff 2 32kw 0001 0000 0001 7fff 2 0000 2000 0000 2fff 1 0000 8000 0000 ffff 1 0000 1000 0000 1fff 0 0000 0000 0000 7fff 0 0000 0000 0000 0fff 32mb, 64mb, 128mb: 3v embedded parallel nor flash memory organization pdf: 09005aef84dc44a7 m29ew_32mb-128mb.pdf - rev. b 11/12 en 15 micron technology, inc. reserves the right to change products or specifications without notice. ? 2012 micron technology, inc. all rights reserved.
table 7: 32mb memory map C x8/x16 uniform blocks [63:0] block block size address range (x8) block block size address range (x16) start end start end 63 64kb 03f 0000h 03f ffffh 63 32kw 01f 8000h 01f ffffh ? ? ? ? ? ? 0 000 0000h 000 ffffh 0 000 0000h 000 7fffh 32mb, 64mb, 128mb: 3v embedded parallel nor flash memory organization pdf: 09005aef84dc44a7 m29ew_32mb-128mb.pdf - rev. b 11/12 en 16 micron technology, inc. reserves the right to change products or specifications without notice. ? 2012 micron technology, inc. all rights reserved.
memory map C 64mb table 8: 64mb memory map C x8 top and bottom boot [134:0] block block size address range (x8 top boot) block block size address range (x8 bottom boot) start end start end 134 8kb 007f e000 007f ffff 134 64kb 007f 0000 007f ffff 133 007f c000 007f dfff 133 007e 0000 007e ffff 132 007f a000 007f bfff 132 007d 0000 007d ffff 131 007f 8000 007f 9fff ? ? ? ? 130 007f 6000 007f 7fff 8 64kb 0001 0000 0001 ffff 129 007f 4000 007f 5fff 7 8kb 0000 e000 0000 ffff 128 007f 2000 007f 3fff 6 0000 c000 0000 dfff 127 007f 0000 007f 1fff 5 0000 a000 0000 bfff 126 64kb 007e 0000 007e ffff 4 0000 8000 0000 9fff ? ? ? ? 3 0000 6000 0000 7fff 2 64kb 0002 0000 0002 ffff 2 0000 4000 0000 5fff 1 0001 0000 0001 ffff 1 0000 2000 0000 3fff 0 0000 0000 0000 ffff 0 0000 0000 0000 1fff table 9: 64mb memory map C x16 top and bottom boot [134:0] block block size address range (x16 top boot) block block size address range (x16 bottom boot) start end start end 134 4kw 003f f000 003f ffff 134 32kw 003f 8000 003f ffff 133 003f e000 003f efff 133 003f 0000 003f 7fff 132 003f d000 003f dfff 132 003e 8000 003e ffff 131 003f c000 003f cfff ? ? ? ? 130 003f b000 003f bfff 8 32kw 0000 8000 0000 ffff 129 003f a000 003f afff 7 4kw 0000 7000 0000 7fff 128 003f 9000 003f 9fff 6 0000 6000 0000 6fff 127 003f 8000 003f 8fff 5 0000 5000 0000 5fff 126 32kw 003f 0000 003f 7fff 4 0000 4000 0000 4fff ? ? ? ? 3 0000 3000 0000 3fff 2 32kw 0001 0000 0001 7fff 2 0000 2000 0000 2fff 1 0000 8000 0000 ffff 1 0000 1000 0000 1fff 0 0000 0000 0000 7fff 0 0000 0000 0000 0fff 32mb, 64mb, 128mb: 3v embedded parallel nor flash memory organization pdf: 09005aef84dc44a7 m29ew_32mb-128mb.pdf - rev. b 11/12 en 17 micron technology, inc. reserves the right to change products or specifications without notice. ? 2012 micron technology, inc. all rights reserved.
table 10: 64mb memory map C x8/x16 uniform blocks [127:0] block block size address range (x8) block block size address range (x16) start end start end 127 64kb 07f 0000h 07f ffffh 127 32kw 03f 8000h 03f ffffh ? ? ? ? ? ? 63 03f 0000h 03f ffffh 63 01f 8000h 01f ffffh ? ? ? ? ? ? 0 000 0000h 000 ffffh 0 000 0000h 000 7fffh 32mb, 64mb, 128mb: 3v embedded parallel nor flash memory organization pdf: 09005aef84dc44a7 m29ew_32mb-128mb.pdf - rev. b 11/12 en 18 micron technology, inc. reserves the right to change products or specifications without notice. ? 2012 micron technology, inc. all rights reserved.
memory map C 128mb table 11: 128mb memory map C x8/x16 uniform blocks [127:0] block block size address range (x8) block block size address range (x16) start end start end 127 128kb 0fe 0000h 0ff ffffh 127 64kw 07f 0000h 07f ffffh ? ? ? ? ? ? 63 07e 0000h 07f ffffh 63 03f 0000h 03f ffffh ? ? ? ? ? ? 0 000 0000h 001 ffffh 0 000 0000h 000 ffffh 32mb, 64mb, 128mb: 3v embedded parallel nor flash memory organization pdf: 09005aef84dc44a7 m29ew_32mb-128mb.pdf - rev. b 11/12 en 19 micron technology, inc. reserves the right to change products or specifications without notice. ? 2012 micron technology, inc. all rights reserved.
bus operations table 12: bus operations notes 1 and 2 apply to entire table operation ce# oe# we# rst# v pp /wp# 8-bit mode 16-bit mode a[max:0], dq15/a-1 dq[14:8] dq[7:0] a[max:0] dq15/a-1, dq[14:0] read l l h h x byte address high-z data output word address data output write l h l h h 3 command address high-z data input 4 command address data input 4 standby h x x h h x high-z high-z x high-z output disable l h h h x x high-z high-z x high-z reset x x x l x x high-z high-z x high-z notes: 1. typical glitches of less than 3ns on ce#, we#, and rst# are ignored by the device and do not affect bus operations. 2. h = logic level high (v ih ); l = logic level low (v il ); x = high or low. 3. if wp# is low, then the highest or the lowest block remains protected, or the top two blocks or the bottom two blocks, depending on line item. 4. data input is required when issuing a command sequence or when performing data polling or block protection. read bus read operations read from the memory cells, registers, or cfi space. to accelerate the read operation, the memory array can be read in page mode where data is inter- nally read and stored in a page buffer. page size is 8 words (16 bytes) and is addressed by address inputs a[2:0] in x16 bus mode and a[2:0] plus dq15/a-1 in x8 bus mode. the extended memory blocks and cfi area do not support page read mode. a valid bus read operation involves setting the desired address on the address inputs, taking ce# and oe# low, and holding we# high. the data i/os will output the value. (see ac characteristics for details about when the output becomes valid.) write bus write operations write to the command interface. a valid bus write operation begins by setting the desired address on the address inputs. the address inputs are latched by the command interface on the falling edge of ce# or we#, whichever occurs last. the data i/os are latched by the command interface on the rising edge of ce# or we#, whichever occurs first. oe# must remain high during the entire bus write oper- ation. (see ac characteristics for timing requirement details.) standby driving ce# high in read mode causes the device to enter standby, and data i/os to be high-z. to reduce the supply current to the standby supply current (i cc2 ), ce# must be held within v cc 0.3v. (see dc characteristics.) 32mb, 64mb, 128mb: 3v embedded parallel nor flash bus operations pdf: 09005aef84dc44a7 m29ew_32mb-128mb.pdf - rev. b 11/12 en 20 micron technology, inc. reserves the right to change products or specifications without notice. ? 2012 micron technology, inc. all rights reserved.
during program or erase operations the device will continue to use the program/ erase supply current (i cc3 ) until the operation completes. output disable data i/os are high-z when oe# is high. reset during reset mode the device is deselected and the outputs are high-z. the device is in reset mode when rst# is low. the power consumption is reduced to the standby level, independently from ce#, oe#, or we# inputs. 32mb, 64mb, 128mb: 3v embedded parallel nor flash bus operations pdf: 09005aef84dc44a7 m29ew_32mb-128mb.pdf - rev. b 11/12 en 21 micron technology, inc. reserves the right to change products or specifications without notice. ? 2012 micron technology, inc. all rights reserved.
registers status register table 13: status register bit definitions note 1 applies to entire table bit name settings description notes dq7 data polling bit 0 or 1, depending on operations monitors whether the program/erase controller has successful- ly completed its operation, or has responded to an erase sus- pend operation. 2, 3, 4 dq6 toggle bit toggles: 0 to 1; 1 to 0; and so on monitors whether the program/erase controller has successful- ly completed its operations, or has responded to an erase suspend operation. during a program/erase operation, dq6 toggles from 0 to 1, 1 to 0, and so on, with each succes- sive read operation from any address. 3, 4, 5 dq5 error bit 0 = success 1 = failure identifies errors detected by the program/erase controller. dq5 is set to 1 when a program, block erase, or chip erase op- eration fails to write the correct data to the memory, or when a blank check operation fails. 4, 6 dq3 erase timer bit 0 = erase not in progress 1 = erase in progress identifies the start of program/erase controller operation dur- ing a block erase command. before the program/erase con- troller starts, this bit set to 0, and additional blocks to be erased can be written to the command interface. 4 dq2 alternative toggle bit toggles: 0 to 1; 1 to 0; and so on monitors the program/erase controller during erase opera- tions. during chip erase, block erase, and erase suspend operations, dq2 toggles from 0 to 1, 1 to 0, and so on, with each successive read operation from addresses within the blocks being erased. 3, 4 dq1 buffered program abort bit 1 = abort indicates a buffer program operation abort. the buffered program abort and reset command must be issued to re- turn the device to read mode (see write to buffer pro- gram command). notes: 1. the status register can be read during program, erase, or erase suspend operations; the read operation outputs data on dq[7:0]. 2. for a program operation in progress, dq7 outputs the complement of the bit being programmed. for a read operation from the address previously programmed success- fully, dq7 outputs existing dq7 data. for a read operation from addresses with blocks to be erased while an erase suspend operation is in progress, dq7 outputs 0; upon successful completion of the erase suspend operation, dq7 outputs 1. for an erase or blank check operation in progress, dq7 outputs 0; upon either operation's successful completion, dq7 outputs 1. 3. after successful completion of a program, erase, or blank check operation, the de- vice returns to read mode. 4. during erase suspend mode, read operations to addresses within blocks not being erased output memory array data as if in read mode. a protected block is treated the same as a block not being erased. see the toggle flowchart for more information. 5. during erase suspend mode, dq6 toggles when addressing a cell within a block being erased. the toggling stops when the program/erase controller has suspended the erase operation. see the toggle flowchart for more information. 32mb, 64mb, 128mb: 3v embedded parallel nor flash registers pdf: 09005aef84dc44a7 m29ew_32mb-128mb.pdf - rev. b 11/12 en 22 micron technology, inc. reserves the right to change products or specifications without notice. ? 2012 micron technology, inc. all rights reserved.
6. when dq5 is set to 1, a read/reset command must be issued before any subsequent command. table 14: operations and corresponding bit settings note 1 applies to entire table operation address dq7 dq6 dq5 dq3 dq2 dq1 ry/by# notes program any address dq7# toggle 0 C C 0 0 2 blank check any address 1 toggle 0 C C 0 0 chip erase any address 0 toggle 0 1 toggle C 0 block erase before time-out erasing block 0 toggle 0 0 toggle C 0 non-erasing block 0 toggle 0 0 no toggle C 0 block erase erasing block 0 toggle 0 1 toggle C 0 non-erasing block 0 toggle 0 1 no toggle C 0 program suspend programming block invalid operation high-z nonprogramming block outputs memory array data as if in read mode high-z erase suspend erasing blk 1 no toggle 0 C toggle C high-z non-erasing blk outputs memory array data as if in read mode high-z program during erase suspend erasing block dq7# toggle 0 C toggle C 0 2 non-erasing block dq7# toggle 0 C no toggle C 0 2 buffered program abort any address dq7# toggle 0 C C 1 high-z program error any address dq7# toggle 1 C C C high-z 2 erase error erase success block 0 toggle 1 1 no toggle C high-z erase fail block 0 toggle 1 1 toggle C high-z blank check er- ror any address 1 toggle 1 1 toggle C high-z notes: 1. unspecified data bits should be ignored. 2. dq7# for buffer program is related to the last address location loaded. 32mb, 64mb, 128mb: 3v embedded parallel nor flash registers pdf: 09005aef84dc44a7 m29ew_32mb-128mb.pdf - rev. b 11/12 en 23 micron technology, inc. reserves the right to change products or specifications without notice. ? 2012 micron technology, inc. all rights reserved.
figure 6: data polling flowchart start dq7 = data dq5 = 1 dq1 = 1 dq7 = data no no no no yes yes yes yes read dq7, dq5, and dq1 at valid address 1 read dq7 at valid address success failure 2 notes: 1. valid address is the address being programmed or an address within the block being erased or on which a blank check operation has been executed. 2. the data polling process does not support the blank check operation. the process represented in the toggle bit flowchart figure can provide information on the blank check operation. 3. failure results: dq5 = 1 indicates an operation error; dq1 = 1 indicates a write to buf- fer program abort operation. 32mb, 64mb, 128mb: 3v embedded parallel nor flash registers pdf: 09005aef84dc44a7 m29ew_32mb-128mb.pdf - rev. b 11/12 en 24 micron technology, inc. reserves the right to change products or specifications without notice. ? 2012 micron technology, inc. all rights reserved.
figure 7: toggle bit flowchart dq6 = toggle dq5 = 1 dq6 = toggle no no yes yes yes start read dq6 at valid address read dq6, dq5, and dq1 at valid address read dq6 (twice) at valid address success failure 1 dq1 = 1 no yes no note: 1. failure results: dq5 = 1 indicates an operation error; dq1 = 1 indicates a write to buf- fer program abort operation. 32mb, 64mb, 128mb: 3v embedded parallel nor flash registers pdf: 09005aef84dc44a7 m29ew_32mb-128mb.pdf - rev. b 11/12 en 25 micron technology, inc. reserves the right to change products or specifications without notice. ? 2012 micron technology, inc. all rights reserved.
figure 8: status register polling flowchart write to buffer program start dq7 = valid data dq5 = 1 yes no no yes yes dq6 = toggling yes no no no yes program operation no no dq6 = toggling no dq2 = toggling yes yes yes dq1 = 1 read 3 correct data? no yes read 1 read 2 read 2 read 3 device busy: repolling device busy: repolling read 3 program operation complete program operation failure write to buffer program abort timeout failure erase operation complete erase/suspend mode device error read2.dq6 = read3.dq6 read2.dq2 = read3.dq2 read1.dq6 = read2.dq6 32mb, 64mb, 128mb: 3v embedded parallel nor flash registers pdf: 09005aef84dc44a7 m29ew_32mb-128mb.pdf - rev. b 11/12 en 26 micron technology, inc. reserves the right to change products or specifications without notice. ? 2012 micron technology, inc. all rights reserved.
lock register table 15: lock register bit definitions note 1 applies to entire table bit name settings description notes dq2 password protection mode lock bit 0 = password protection mode enabled 1 = password protection mode disabled (default) places the device permanently in password protection mode. 2 dq1 nonvolatile protection mode lock bit 0 = nonvolatile protection mode enabled with pass- word protection mode permanently disabled 1 = nonvolatile protection mode enabled (default) places the device in nonvolatile protection mode with pass- word protection mode permanently disabled. when shipped from the factory, the device will operate in nonvolatile protec- tion mode, and the memory blocks are unprotected. 2 dq0 extended memory block protection bit 0 = protected 1 = unprotected (default) if the device is shipped with the extended memory block un- locked, the block can be protected by setting this bit to 0. the extended memory block protection status can be read in auto select mode by issuing an auto select command. notes: 1. the lock register is a 16-bit, one-time programmable register. dq[15:3] are reserved and are set to a default value of 1. 2. the password protection mode lock bit and nonvolatile protection mode lock bit cannot both be programmed to 0. any attempt to program one while the other is programmed causes the operation to abort, and the device returns to read mode. the device is ship- ped from the factory with the default setting. table 16: block protection status nonvolatile protection bit lock bit 1 nonvolatile protection bit 2 volatile protection bit 3 block protection status block protection status 1 1 1 00h block unprotected; nonvolatile protection bit changea- ble. 1 1 0 01h block protected by volatile protection bit; nonvolatile protection bit changeable. 1 0 1 01h block protected by nonvolatile protection bit; nonvola- tile protection bit changeable. 1 0 0 01h block protected by nonvolatile protection bit and vola- tile protection bit; nonvolatile protection bit changea- ble. 0 1 1 00h block unprotected; nonvolatile protection bit un- changeable. 0 1 0 01h block protected by volatile protection bit; nonvolatile protection bit unchangeable. 0 0 1 01h block protected by nonvolatile protection bit; nonvola- tile protection bit unchangeable. 32mb, 64mb, 128mb: 3v embedded parallel nor flash registers pdf: 09005aef84dc44a7 m29ew_32mb-128mb.pdf - rev. b 11/12 en 27 micron technology, inc. reserves the right to change products or specifications without notice. ? 2012 micron technology, inc. all rights reserved.
table 16: block protection status (continued) nonvolatile protection bit lock bit 1 nonvolatile protection bit 2 volatile protection bit 3 block protection status block protection status 0 0 0 01h block protected by nonvolatile protection bit and vola- tile protection bit; nonvolatile protection bit unchange- able. notes: 1. nonvolatile protection bit lock bit: when cleared to 1, all nonvolatile protection bits are unlocked; when set to 0, all nonvolatile protection bits are locked. 2. block nonvolatile protection bit: when cleared to 1, the block is unprotected; when set to 0, the block is protected. 3. block volatile protection bit: when cleared to 1, the block is unprotected; when set to 0, the block is protected. figure 9: lock register program flowchart start done? dq5 = 1 no no yes yes enter lock register command set address-data (unlock) cycle 1 address-data (unlock) cycle 2 address-data cycle 3 program lock register address-data cycle 1 address-data cycle 2 polling algorithm success: exit protection command set (returns to device read mode) address-data cycle 1 address-data cycle 2 failure: read/reset (returns device to read mode) 32mb, 64mb, 128mb: 3v embedded parallel nor flash registers pdf: 09005aef84dc44a7 m29ew_32mb-128mb.pdf - rev. b 11/12 en 28 micron technology, inc. reserves the right to change products or specifications without notice. ? 2012 micron technology, inc. all rights reserved.
notes: 1. each lock register bit can be programmed only once. 2. see the block protection command definitions table for address-data cycle details. 32mb, 64mb, 128mb: 3v embedded parallel nor flash registers pdf: 09005aef84dc44a7 m29ew_32mb-128mb.pdf - rev. b 11/12 en 29 micron technology, inc. reserves the right to change products or specifications without notice. ? 2012 micron technology, inc. all rights reserved.
standard command definitions C address-data cycles table 17: standard command definitions C address-data cycles, 8-bit and 16-bit note 1 applies to entire table command and code/subcode bus size address and data cycles notes 1st 2nd 3rd 4th 5th 6th a d a d a d a d a d a d read and auto select operations read/reset (f0h) x8 x f0 aaa aa 555 55 x f0 x16 x f0 555 aa 2aa 55 x f0 read cfi (98h) x8 aa 98 x16 55 auto select (90h) x8 aaa aa 555 55 aaa 90 note 2 note 2 2, 3, 4 x16 555 2aa 555 bypass operations unlock bypass (20h) x8 aaa aa 555 55 aaa 20 x16 555 2aa 555 unlock bypass reset (90h/00h) x8 x 90 x 00 x16 program operations program (a0h) x8 aaa aa 555 55 aaa a0 pa pd x16 555 2aa 555 unlock bypass program (a0h) x8 x a0 pa pd 6 x16 double byte/word program (50h) x8 aaa 50 pa2 pd x16 555 quadruple byte/ word program (56h) x8 aaa 56 pa4 pd x16 555 octuple byte pro- gram (8bh) x8 aaa 8b pa8 pd 5 write to buffer program (25h) x8 aaa aa 555 55 bad 25 bad n pa pd 7, 8, 9 x16 555 2aa enhanced write to buffer program (33h) x16 555 aa 2aa 55 bad 33 pa pd 7, 9, 10 unlock bypass write to buffer program (25h) x8 bad 25 bad n pa pd 5 x16 32mb, 64mb, 128mb: 3v embedded parallel nor flash standard command definitions C address-data cycles pdf: 09005aef84dc44a7 m29ew_32mb-128mb.pdf - rev. b 11/12 en 30 micron technology, inc. reserves the right to change products or specifications without notice. ? 2012 micron technology, inc. all rights reserved.
table 17: standard command definitions C address-data cycles, 8-bit and 16-bit (continued) note 1 applies to entire table command and code/subcode bus size address and data cycles notes 1st 2nd 3rd 4th 5th 6th a d a d a d a d a d a d unlock bypass enhanced write to buffer program (33h) x16 bad 33 pa pd 10 write to buffer program confirm (29h) x8 bad 29 x16 enhanced write to buffer program confirm (29h) x8 bad 29 x16 buffered program abort and reset (f0h) x8 aaa aa 555 55 aaa f0 x16 555 2aa 555 program suspend (b0h) x8 x b0 x16 program resume (30h) x8 x 30 x16 erase operations chip erase (80/10h) x8 aaa aa 555 55 aaa 80 aaa aa 555 55 aaa 10 x16 555 2aa 555 555 2aa 555 unlock bypass chip erase (80/10h) x8 x 80 x 10 5 x16 block erase (80/30h) x8 aaa aa 555 55 aaa 80 aaa aa 555 55 bad 30 11 x16 555 2aa 555 555 2aa unlock bypass block erase (80/30h) x8 x 80 bad 30 5 x16 erase suspend (b0h) x8 x b0 x16 erase resume (30h) x8 x 30 x16 blank check operations blank check setup (eb/76h) x8 aaa aa 555 55 bad eb bad 76 bad 00 bad 00 x16 555 2aa blank check confirm and read (29h) x8 bad 29 bad note 2 2 x16 notes: 1. a = address; d = data; x = "don't care;" bad = any address in the block; n = number of bytes to be programmed; pa = program address; pa2 = program address with constant amax:a0 for x8 or amax:a1 for x16, which should be used two times to select adjacent 32mb, 64mb, 128mb: 3v embedded parallel nor flash standard command definitions C address-data cycles pdf: 09005aef84dc44a7 m29ew_32mb-128mb.pdf - rev. b 11/12 en 31 micron technology, inc. reserves the right to change products or specifications without notice. ? 2012 micron technology, inc. all rights reserved.
two bytes/words; pa4 = program address with constant amax:a1 for x8 or amax:a2 for x16, which should be used four times to select adjacent four bytes/words; pa8 = pro- gram address with constant amax:a2 for x8, which should be used eight times to select adjacent eight bytes; pd = program data; gray shading = not applicable. all values in the table are hexadecimal. some commands require both a command code and sub- code. 2. these cells represent read cycles (versus write cycles for the others). 3. auto select enables the device to read the manufacturer code, device code, block pro- tection status, and extended memory block protection indicator. 4. auto select addresses and data are specified in the electronic signature table and the extended memory block protection table. 5. for any unlock bypass erase/program command, the first two unlock cycles are unnecessary. 6. this command is only for x8 devices. 7. bad must be the same as the address loaded during the write to buffer program 3rd and 4th cycles. 8. write to buffer program operation: maximum cycles = 261 (x8) and 261 (x16). un- lock bypass write to buffer program operation: maximum cycles = 259 (x8), 259 (x16). write to buffer program operation: n + 1 = bytes to be programmed; maxi- mum buffer size = 256 bytes (x8) and 512 bytes (x16). 9. for x8, a[max:7] address pins should remain unchanged while a[6:0] and a-1 pins are used to select a byte within the n + 1 byte page. for x16, a[max:8] address pins should remain unchanged while a[7:0] pins are used to select a word within the n+1 word page. 10. this command is only for x16 devices. for enhanced write to buffer program op- eration, total cycles = 259. for unlock bypass enhanced write to buffer pro- gram operation, total cycles = 257. 11. block erase address cycles can extend beyond six address-data cycles, depending on the number of blocks to erase. 32mb, 64mb, 128mb: 3v embedded parallel nor flash standard command definitions C address-data cycles pdf: 09005aef84dc44a7 m29ew_32mb-128mb.pdf - rev. b 11/12 en 32 micron technology, inc. reserves the right to change products or specifications without notice. ? 2012 micron technology, inc. all rights reserved.
read and auto select operations read/reset command the read/reset (f0h) command returns the device to read mode and resets the errors in the status register. one or three bus write operations can be used to issue the read/reset command. to return the device to read mode, this command can be issued between bus write cycles before the start of a program or erase operation. if the read/reset com- mand is issued during the timeout of a block erase operation, the device requires up to 10 s to abort, during which time no valid data can be read. this command will not abort an erase operation while in erase suspend. read cfi command the read cfi (98h) command puts the device in read cfi mode and is only valid when the device is in read array or auto select mode. one bus write cycle is required to issue the command. once in read cfi mode, bus read operations will output data from the cfi memory area (refer to the common flash interface for details). a read/reset command must be issued to return the device to the previous mode (read array or auto select ). a sec- ond read/reset command is required to put the device in read array mode from auto select mode. auto select command at power-up or after a hardware reset, the device is in read mode. it can then be put in auto select mode by issuing an auto select (90h) command. auto select mode ena- bles the following device information to be read: ? electronic signature, which includes manufacturer and device code information as shown in the electronic signature table. ? block protection, which includes the block protection status and extended memory block protection indicator, as shown in the block protection table. electronic signature or block protection information is read by executing a read opera- tion with control signals and addresses set, as shown in the read electronic signature table or the block protection table, respectively. in addition, this device information can be read or set by issuing an auto select command. auto select mode can be used by the programming equipment to automatically match a device with the application code to be programmed. three consecutive bus write operations are required to issue an auto select com- mand. the device remains in auto select mode until a read/reset or read cfi com- mand is issued. the device cannot enter auto select mode when a program or erase operation is in progress (ry/by# low). however, auto select mode can be entered if the program or erase operation has been suspended by issuing a program suspend or erase sus- pend command. 32mb, 64mb, 128mb: 3v embedded parallel nor flash read and auto select operations pdf: 09005aef84dc44a7 m29ew_32mb-128mb.pdf - rev. b 11/12 en 33 micron technology, inc. reserves the right to change products or specifications without notice. ? 2012 micron technology, inc. all rights reserved.
auto select mode is exited by performing a reset. the device returns to read mode un- less it entered auto select mode after an erase suspend or program suspend command, in which case it returns to erase or program suspend mode. table 18: read electronic signature note 1 applies to entire table read cycle ce# oe# we# address input data input/output 8-bit/16-bit 8-bit only 8-bit only 16-bit only a[max:11] a[10:4] a3 a2 a1 a0 a-1 dq[14:8] dq[7:0] dq[15:0] manufacturer code l l h x l l l l l x x 89h 0089h device code 1 l l h x l l l l h x x 7eh 227eh device code 2 128mb l l h x l h h h l x x 21h 2221h 64mb boot 10h 2210h 64mb uniform 0ch 220ch 32mb boot 1ah 221ah 32mb uniform 1dh 221dh device code 3 128mb uniform l l h x l h h h h x x 01h 2201h 64mb uniform 64mb top 32mb top device code 3 64mb bottom l l h x l h h h h x x 00h 2200h 32mb bottom 32mb uniform note: 1. h = logic level high (v ih ); l = logic level low (v il ); x = high or low. 32mb, 64mb, 128mb: 3v embedded parallel nor flash read and auto select operations pdf: 09005aef84dc44a7 m29ew_32mb-128mb.pdf - rev. b 11/12 en 34 micron technology, inc. reserves the right to change products or specifications without notice. ? 2012 micron technology, inc. all rights reserved.
table 19: block protection note 1 applies to entire table read cycle ce# oe# we# address input data input/output 8-bit/16-bit 8-bit only 8-bit only 16-bit only a[max:15] a[14:11] a[10:2] a1 a0 a-1 dq[14:8] dq[7:0] dq[15:0] extended memory block protection indicator (dq7) m29ewl 128mb l l h x x l h h x x 89h 2 0089h 2 09h 3 0009h 3 m29ewh 128mb l l h x x l h h x x 99h 2 0099h 2 19h 3 0019h 3 m29ewl 64mb 32mb l l h x x l h h x x 8ah 2 008ah 2 0ah 3 000ah 3 m29ewh 64mb 32mb l l h x x l h h x x 9ah 2 009ah 2 1ah 3 001ah 3 m29ewb 64mb 32mb l l h x x l h h x x 8ah 2 008ah 2 0ah 3 000ah 3 m29ewt 64mb 32mb l l h x x l h h x x 9ah 2 009ah 2 1ah 3 001ah 3 block protection status l l h block base address 6 l l h l x x 01h 4 0001h 4 00h 5 0000h 5 notes: 1. h = logic level high (v ih ); l = logic level low (v il ); x = high or low. 2. micron-prelocked (permanent). 3. customer-lockable. 4. protected: 01h (in x8 mode) is output on dq[7:0]. 5. unprotected: 00h (in x8 mode) is output on dq[7:0]. 6. block base address for 128mb device, should be a[max:16], while a15 = x. bypass operations unlock bypass command the unlock bypass (20h) command is used to place the device in unlock bypass mode. three bus write operations are required to issue the unlock bypass com- mand. when the device enters unlock bypass mode, the two initial unlock cycles required for a standard program or erase operation are not needed, thus enabling faster total program or erase time. the unlock bypass command is used in conjunction with unlock bypass pro- gram or unlock bypass erase commands to program or erase the device faster than with standard program or erase commands. when the cycle time to the device 32mb, 64mb, 128mb: 3v embedded parallel nor flash bypass operations pdf: 09005aef84dc44a7 m29ew_32mb-128mb.pdf - rev. b 11/12 en 35 micron technology, inc. reserves the right to change products or specifications without notice. ? 2012 micron technology, inc. all rights reserved.
is long, considerable time savings can be gained by using these commands. when in unlock bypass mode, only the following commands are valid: ? the unlock bypass program command can be issued to program addresses within the device. ? the unlock bypass block erase command can then be issued to erase one or more memory blocks. ? the unlock bypass chip erase command can be issued to erase the whole mem- ory array. ? the unlock bypass write to buffer program and unlock bypass en- hanced write to buffer program commands can be issued to speed up the programming operation. ? the unlock bypass reset command can be issued to return the device to read mode. in unlock bypass mode, the device can be read as if in read mode. in addition to the unlock bypass command, when v pp /wp# is raised to v pph , the de- vice automatically enters unlock bypass mode. when v pp /wp# returns to v ih or v il , the device is no longer in unlock bypass mode and normal operation resumes. the transi- tions from v ih to v pph and from v pph to v ih must be slower than t vhvpp (see the accel- erated program, data polling/toggle ac characteristics). note: micron recommends the user enter and exit unlock bypass mode using enter unlock bypass and unlock bypass reset commands rather than raising v pp /wp# to v pph . v pp /wp# should never be raised to v pph from any mode except read mode; oth- erwise, the device may be left in an indeterminate state. unlock bypass reset command the unlock bypass reset (90/00h) command is used to return to read/reset mode from unlock bypass mode. two bus write operations are required to issue the un- lock bypass reset command. the read/reset command does not exit from un- lock bypass mode. program operations program command the program (a0h) command can be used to program a value to one address in the memory array. the command requires four bus write operations, and the final write operation latches the address and data in the internal state machine and starts the pro- gram/erase controller. after programming has started, bus read operations output the status register content. programming can be suspended and then resumed by issuing a program suspend command and a program resume command, respectively. if the address falls in a protected block, the program command is ignored, and the data remains unchanged. the status register is not read, and no error condition is given. after the program operation has completed, the device returns to read mode, unless an error has occurred. when an error occurs, bus read operations to the device contin- 32mb, 64mb, 128mb: 3v embedded parallel nor flash program operations pdf: 09005aef84dc44a7 m29ew_32mb-128mb.pdf - rev. b 11/12 en 36 micron technology, inc. reserves the right to change products or specifications without notice. ? 2012 micron technology, inc. all rights reserved.
ue to output the status register. a read/reset command must be issued to reset the error condition and return the device to read mode. the program command cannot change a bit set to 0 back to 1, and an attempt to do so is masked during a program operation. instead, an erase command must be used to set all bits in one memory block or in the entire memory from 0 to 1. the program operation is aborted by performing a reset or by powering-down the de- vice. in this case, data integrity cannot be ensured, and it is recommended that the words or bytes that were aborted be reprogrammed. unlock bypass program command when the device is in unlock bypass mode, the unlock bypass program (a0h) command can be used to program one address in the memory array. the command re- quires two bus write operations instead of four required by a standard program command; the final write operation latches the address and data and starts the pro- gram/erase controller (the standard program command requires four bus write op- erations). the program operation using the unlock bypass program command behaves identically to the program operation using the program command. the operation cannot be aborted. a bus read operation to the memory outputs the status register. double byte/word program command the double byte/word program (50h) command is used to write a page of two adjacent bytes/words in parallel. the two bytes/words must differ only for the address a-1 or a0, respectively. three bus write cycles are necessary to issue the command: the first bus cycle sets up the command, the second bus cycle latches the address and data of the first byte/word to be programmed, and the third bus cycle latches the address and data of the second byte/word to be programmed and starts the program/erase con- troller. note: the double byte/word program command is available only in the 32mb and 64mb devices; also only v ppl is to be applied to the v pp /wp# pin. quadruple byte/word program command the quadruple byte/word program (56h) command is used to write a page of four adjacent bytes/words in parallel. the four bytes/words must differ for addresses a0, dq15/a-1 in x8 mode or for addresses a1, a0 in x16 mode. five bus write cycles are necessary to issue the command: the first bus cycle sets up the command, the second bus cycle latches the address and data of the first byte/word to be programmed, the third bus cycle latches the address and data of the second byte/word to be program- med, the fourth bus cycle latches the address and data of the third byte/word to be pro- grammed, and the fifth bus cycle latches the address and data of the fourth byte/word to be programmed and starts the program/erase controller. note: the quadruple byte/word program command is available only in the 32mb and 64mb devices; also only v ppl is to be applied to the v pp /wp# pin. 32mb, 64mb, 128mb: 3v embedded parallel nor flash program operations pdf: 09005aef84dc44a7 m29ew_32mb-128mb.pdf - rev. b 11/12 en 37 micron technology, inc. reserves the right to change products or specifications without notice. ? 2012 micron technology, inc. all rights reserved.
octuple byte program command the octuple byte program (8bh) command is used to write a page of eight adja- cent bytes in parallel. the eight bytes must differ for addresses a1, a0, dq15/a-1 in x8 mode only. nine bus write cycles are necessary to issue the command: the first bus cycle sets up the command, the second bus cycle latches the address and data of the first byte to be programmed, the third bus cycle latches the address and data of the second byte to be programmed, the fourth bus cycle latches the address and data of the third byte to be programmed, the fifth bus cycle latches the address and data of the fourth byte to be programmed, the sixth bus cycle latches the address and data of the fifth byte to be pro- grammed, the seventh bus cycle latches the address and data of the sixth byte to be pro- grammed, the eighth bus cycle latches the address and data of the seventh byte to be programmed, and the ninth bus cycle latches the address and data of the eighth byte to be programmed, and starts the program/erase controller. note: the octuple byte program command is available only in the 32mb and 64mb x8 devices; also only v ppl is to be applied to the v pp /wp# pin. write to buffer program command the write to buffer program (25h) command makes use of the program buffer to speed up programming and dramatically reduces system programming time compared to the standard non-buffered program command. 32mb through 128mb devices sup- port a 256-word maximum program buffer. when issuing a write to buffer program command, v pp /wp# can be held high or raised to v pph . also, it can be held low if the block is not the lowest or highest block or the top/bottom two blocks, depending on the part number. when v pph is applied to the v pp /wp# pin during execution of the command, programming speed increases (see the accelerated program, data polling/toggle ac characteristics section). the following successive steps are required to issue the write to buffer program command: first, two unlock cycles are issued. next, a third bus write cycle sets up the write to buffer program command. the set-up code can be addressed to any location within the targeted block. then, a fourth bus write cycle sets up the number of words/ bytes to be programmed. value n is written to the same block address, where n + 1 is the number of words/bytes to be programmed. value n + 1 must not exceed the size of the program buffer, or the operation will abort. a fifth cycle loads the first address and data to be programmed. last, n bus write cycles load the address and data for each word/ byte into the program buffer. addresses must lie within the range from the start address +1 to the start address + (n - 1) . optimum programming performance and lower power usage are achieved by aligning the starting address at the beginning of a 256-word boundary (a[7:0] = 0x000h). any buffer size smaller than 256 words is allowed within a 256-word boundary, while all ad- dresses used in the operation must lie within the 256-word boundary. in addition, any crossing boundary buffer program will result in a program abort. for a x8 device, maxi- mum buffer size is 256 bytes; for a x16 device, the maximum buffer size is 512 bytes. to program the content of the program buffer, this command must be followed by a write to buffer program confirm command. 32mb, 64mb, 128mb: 3v embedded parallel nor flash program operations pdf: 09005aef84dc44a7 m29ew_32mb-128mb.pdf - rev. b 11/12 en 38 micron technology, inc. reserves the right to change products or specifications without notice. ? 2012 micron technology, inc. all rights reserved.
if an address is written several times during a write to buffer program operation, the address/data counter will be decremented at each data load operation, and the data will be programmed to the last word loaded into the buffer. invalid address combinations or the incorrect sequence of bus write cycles will abort the write to buffer program command. the status register bits dq1, dq5, dq6, dq7 can be used to monitor the device status during a write to buffer program operation. the write to buffer program command should not be used to change a bit set to 0 back to 1, and an attempt to do so is masked during the operation. rather than the write to buffer program command, the erase command should be used to set memory bits from 0 to 1. figure 10: boundary condition of program buffer size a n y b u f f e r p r o g r a m a t te m p t i s n o t a l l o w e d 0200h 256-word program buffer is allowed 256-word program buffer is allowed 255 words or less are allowed in the program buffer 0000h 256 words 256 words 0100h 32mb, 64mb, 128mb: 3v embedded parallel nor flash program operations pdf: 09005aef84dc44a7 m29ew_32mb-128mb.pdf - rev. b 11/12 en 39 micron technology, inc. reserves the right to change products or specifications without notice. ? 2012 micron technology, inc. all rights reserved.
figure 11: write to buffer program flowchart abort write to buffer write buffer data, start address start x = n write n, 1 block address write to buffer and program aborted 2 write to a different block address x = 0 write next data, 3 program address pair write to buffer confirm, block address x = x - 1 yes no yes no dq7 = data no yes dq5 = 1 yes no dq1 = 1 no yes write to buffer command, block address read status register (dq1, dq5, dq7) at last loaded address dq7 = data 4 no yes check status register (dq5, dq7) at last loaded address fail or abort 5 end first three cycles of the write to buffer program command notes: 1. n + 1 is the number of addresses to be programmed. 2. the buffered program abort and reset command must be issued to return the de- vice to read mode. 3. when the block address is specified, any address in the selected block address space is acceptable. however, when loading program buffer address with data, all addresses must fall within the selected program buffer page. 4. dq7 must be checked because dq5 and dq7 may change simultaneously. 5. if this flowchart location is reached because dq5 = 1, then the write to buffer pro- gram command failed. if this flowchart location is reached because dq1 = 1, then the write to buffer program command aborted. in both cases, the appropriate reset command must be issued to return the device to read mode: a reset command if the operation failed; a write to buffer program abort and reset command if the op- eration aborted. 6. see the standard command definitions C address-data cycles, 8-bit and 16-bit table for details about the write to buffer program command sequence. unlock bypass write to buffer program command when the device is in unlock bypass mode, the unlock bypass write to buffer (25h) command can be used to program the device in fast program mode. the com- 32mb, 64mb, 128mb: 3v embedded parallel nor flash program operations pdf: 09005aef84dc44a7 m29ew_32mb-128mb.pdf - rev. b 11/12 en 40 micron technology, inc. reserves the right to change products or specifications without notice. ? 2012 micron technology, inc. all rights reserved.
mand requires two bus write operations fewer than the standard write to buffer program command. the unlock bypass write to buffer program command behaves the same way as the write to buffer program command: the operation cannot be aborted, and a bus read operation to the memory outputs the status register. the write to buffer program confirm command is used to confirm an un- lock bypass write to buffer program command and to program the n + 1 words/bytes loaded in the program buffer by this command. enhanced write to buffer program command the enhanced write to buffer program (33h) command enables loading 256 words into the writer buffer to reduce system programming time. each write buffer has the same a[22:8] addresses. execution speed is identical to the 256-word write to buffer program speed (see the program/erase characteristics table for details). when issuing this command, the v pp /wp# pin can be held high or raised to v pph (pro- gramming acceleration). note: the enhanced write to buffer program command is available only in the 128mb x16 device, the following successive steps are required to issue the command: two unlock cycles begin the command, followed by a third bus write cycle that sets up the command with setup code that can be addressed to any location within the targeted block. the fourth bus write cycle loads the first address and data to be programmed. there are a total of 256 address and data loading cycles. the command must be followed by an enhanced write to buffer program confirm command to program the buffer content, which confirm cycle ends the command. note that address/data cycles must be loaded in an increasing address order (a[7:0] from 00h to ffh) that includes all 256 words. invalid address combinations or the cor- rect sequence of bus write cycles will result in an abort. status register bits dq1, dq5, dq6, and dq7 enable monitoring the device status dur- ing operation. a 12v external supply can be used to improve programming efficiency. the enhanced write to buffer program command should not be used to change a bit set to 0 back to 1. any attempt to do so is masked during the operation. the erase command should be used to set memory bits from 0 to 1. unlock bypass enhanced write to buffer program command the unlock bypass enhanced write to buffer program (33h)command can be used to program the memory in fast program mode. the command requires two ad- dress/data loading cycles less than the regular enhanced write to buffer pro- gram command. this command behaves identically to the enhanced write to buffer program command. the operation cannot be aborted and a bus read opera- tion to the memory outputs the status register. this command is confirmed by the en- hanced write to buffer program confirm command, which programs the 256 words loaded in the buffer. 32mb, 64mb, 128mb: 3v embedded parallel nor flash program operations pdf: 09005aef84dc44a7 m29ew_32mb-128mb.pdf - rev. b 11/12 en 41 micron technology, inc. reserves the right to change products or specifications without notice. ? 2012 micron technology, inc. all rights reserved.
write to buffer program confirm command the write to buffer program confirm (29h) command is used to confirm a write to buffer program command and to program the n + 1 words/bytes loaded in the program buffer by this command. enhanced write to buffer program confirm command the enhanced write to buffer program confirm (29h) command is used to confirm an enhanced write to buffer program command and to program the 256 words loaded in the buffer. buffered program abort and reset command a buffered program abort and reset (f0h) command must be issued to reset the device to read mode when the buffer program operation is aborted. the buffer programming sequence can be aborted in the following ways: ? load a value that is greater than the page buffer size during the number of locations to program in the write to buffer program command. ? write to an address in a different block than the one specified during the write buf- fer load command. ? write an address/data pair to a different write buffer page than the one selected by the starting address during the program buffer data loading stage of the operation. ? write data other than the confirm command after the specified number of data load cycles. the abort condition is indicated by dq1 = 1, dq7 = dq7# (for the last address location loaded), dq6 = toggle, and dq5 = 0 (all of which are status register bits). a buffered program abort and reset command sequence must be written to reset the device for the next operation. note: the full three-cycle buffered program abort and reset command se- quence is required when using buffer programming features in unlock bypass mode. program suspend command the program suspend (b0h) command can be used to interrupt a program opera- tion so that data can be read from any block. when the program suspend command is issued during a program operation, the device suspends the operation within the pro- gram suspend latency time and updates the status register bits. after the program operation has been suspended, data can be read from any address. however, data is invalid when read from an address where a program operation has been suspended. the program suspend command may also be issued during a program operation while an erase is suspended. in this case, data may be read from any address not in erase suspend or program suspend mode. to read from the extended memory block area (one-time programmable area), the enter/exit extended memory block command sequences must be issued. the system may also issue the auto select command sequence when the device is in program suspend mode. the system can read as many auto select codes as required. 32mb, 64mb, 128mb: 3v embedded parallel nor flash program operations pdf: 09005aef84dc44a7 m29ew_32mb-128mb.pdf - rev. b 11/12 en 42 micron technology, inc. reserves the right to change products or specifications without notice. ? 2012 micron technology, inc. all rights reserved.
when the device exits auto select mode, the device reverts to program suspend mode and is ready for another valid operation. the program suspend operation is aborted by performing a device reset or power- down. in this case, data integrity cannot be ensured, and it is recommended that the words or bytes that were aborted be reprogrammed. program resume command the program resume (30h) command must be issued to exit a program suspend mode and resume a program operation. the controller can use dq7 or dq6 status bits to determine the status of the program operation. after a program resume command is issued, subsequent program resume commands are ignored. another program suspend command can be issued after the device has resumed program- ming. erase operations chip erase command the chip erase (80/10h) command erases the entire chip. six bus write operations are required to issue the command and start the program/erase controller. protected blocks are not erased. if all blocks are protected, the chip erase operation appears to start, but will terminate within approximately100 s, leaving the data un- changed. no error is reported when protected blocks are not erased. during the chip erase operation, the device ignores all other commands, including erase suspend. it is not possible to abort the operation. all bus read operations dur- ing chip erase output the status register on the data i/os. see the status register sec- tion for more details. after the chip erase operation completes, the device returns to read mode, unless an error has occurred. if an error occurs, the device will continue to output the status regis- ter. a read/reset command must be issued to reset the error condition and return to read mode. the chip erase command sets all of the bits in unprotected blocks of the device to 1. all previous data is lost. the operation is aborted by performing a reset or by powering-down the device. in this case, data integrity cannot be ensured, and it is recommended that the entire chip be erased again. unlock bypass chip erase command when the device is in unlock bypass mode, the unlock bypass chip erase (80/10h) command can be used to erase all memory blocks at one time. the command requires only two bus write operations instead of six using the standard chip erase com- mand. the final bus write operation starts the program/erase controller. the unlock bypass chip erase command behaves the same way as the chip erase command: the operation cannot be aborted, and a bus read operation to the memory outputs the status register. 32mb, 64mb, 128mb: 3v embedded parallel nor flash erase operations pdf: 09005aef84dc44a7 m29ew_32mb-128mb.pdf - rev. b 11/12 en 43 micron technology, inc. reserves the right to change products or specifications without notice. ? 2012 micron technology, inc. all rights reserved.
block erase command the block erase (80/30h) command erases a list of one or more blocks. it sets all of the bits in the unprotected selected blocks to 1. all previous data in the selected blocks is lost. six bus write operations are required to select the first block in the list. each addition- al block in the list can be selected by repeating the sixth bus write operation using the address of the additional block. after the command sequence is written, a block erase timeout occurs. during the timeout period, additional block addresses and block erase commands can be written. after the program/erase controller has started, it is not possible to select any more blocks. each additional block must therefore be selected within the timeout period of the last block. the timeout timer restarts when an addi- tional block is selected. after the sixth bus write operation, a bus read operation out- puts the status register. see the we#-controlled program waveforms for details on how to identify if the program/erase controller has started the block erase operation. after the block erase operation completes, the device returns to read mode, unless an error has occurred. if an error occurs, bus read operations will continue to output the status register. a read/reset command must be issued to reset the error condi- tion and return to read mode. if any selected blocks are protected, they are ignored, and all the other selected blocks are erased. if all of the selected blocks are protected, the block erase operation ap- pears to start, but will terminate within approximately100 s, leaving the data un- changed. no error condition is given when protected blocks are not erased. during the block erase operation, the device ignores all commands except the erase suspend command and the read/reset command, which is accepted only during the timeout period. the operation is aborted by performing a reset or powering- down the device. in this case, data integrity cannot be ensured, and it is recommended that the aborted blocks be erased again. unlock bypass block erase command when the device is in unlock bypass mode, the unlock bypass block erase (80/30h) command can be used to erase one or more memory blocks at a time. the command requires two bus write operations instead of six using the standard block erase command. the final bus write operation latches the address of the block and starts the program/erase controller. to erase multiple blocks (after the first two bus write operations have selected the first block in the list), each additional block in the list can be selected by repeating the sec- ond bus write operation using the address of the additional block. the unlock bypass block erase command behaves the same way as the block erase command: the operation cannot be aborted, and a bus read operation to the memory outputs the status register. see the block erase command section for de- tails. erase suspend command the erase suspend (b0h) command temporarily suspends a block erase opera- tion. one bus write operation is required to issue the command. the block address is "don't care." 32mb, 64mb, 128mb: 3v embedded parallel nor flash erase operations pdf: 09005aef84dc44a7 m29ew_32mb-128mb.pdf - rev. b 11/12 en 44 micron technology, inc. reserves the right to change products or specifications without notice. ? 2012 micron technology, inc. all rights reserved.
the program/erase controller suspends the erase operation within the erase suspend latency time of the erase suspend command being issued. however, when the erase suspend command is written during the block erase timeout, the device im- mediately terminates the timeout period and suspends the erase operation. after the program/erase controller has stopped, the device operates in read mode, and the erase is suspended. during an erase suspend operation, it is possible to read and execute program op- erations or write to buffer program operations in blocks that are not suspended. both read and program operations behave normally on these blocks. reading from blocks that are suspended will output the status register. if any attempt is made to pro- gram in a protected block or in the suspended block, the program command is ignor- ed, and the data remains unchanged. in this case, the status register is not read, and no error condition is given. it is also possible to issue auto select, read cfi, and unlock bypass commands during an erase suspend operation. the read/reset command must be issued to return the device to read array mode before the resume command will be accepted. during an erase suspend operation, a bus read operation to the extended memory block will output the extended memory block data. after the device enters extended memory block mode, the exit extended memory block command must be issued before the erase operation can be resumed. an erase suspend command is ignored if it is written during a chip erase opera- tion. if the erase suspend operation is aborted by performing a device reset or power- down, data integrity cannot be ensured, and it is recommended that the suspended blocks be erased again. erase resume command the erase resume (30h) command restarts the program/erase controller after an erase suspend operation. the device must be in read array mode before the resume command will be accepted. an erase can be suspended and resumed more than once. blank check operation blank check commands two commands are required to execute a blank check operation: blank check setup (eb/76h) and blank check confirm and read (29h). the blank check operation determines whether a specified block is blank (that is, completely erased). it can also be used to determine whether a previous erase opera- tion was successful, including erase operations that might have been interrupted by power loss. the blank check operation checks for cells that are programmed or over-erased. if it finds any, it returns a failure status, indicating that the block is not blank. if it returns a passing status, the block is guaranteed blank (all 1s) and is ready to program. 32mb, 64mb, 128mb: 3v embedded parallel nor flash blank check operation pdf: 09005aef84dc44a7 m29ew_32mb-128mb.pdf - rev. b 11/12 en 45 micron technology, inc. reserves the right to change products or specifications without notice. ? 2012 micron technology, inc. all rights reserved.
before executing, the erase operation initiates a blank check operation, and if the target block is blank, the erase operation is skipped, benefitting overall cycle perform- ance; otherwise, the erase operation continues. the blank check operation can occur in only one block at a time, and during its exe- cution, reading the status register is the only other operation allowed. reading from any address in the device enables reading the status register to monitor blank check pro- gress or errors. operations such as read (array data), program, erase, and any sus- pended operation are not allowed. after the blank check operation has completed, the device returns to read mode un- less an error has occurred. when an error occurs, the device continues to output status register data. a read/reset command must be issued to reset the error condition and return the device to read mode. 32mb, 64mb, 128mb: 3v embedded parallel nor flash blank check operation pdf: 09005aef84dc44a7 m29ew_32mb-128mb.pdf - rev. b 11/12 en 46 micron technology, inc. reserves the right to change products or specifications without notice. ? 2012 micron technology, inc. all rights reserved.
block protection command definitions C address-data cycles table 20: block protection command definitions C address-data cycles, 8-bit and 16-bit notes 1 and 2 apply to entire table command and code/subcode bus size address and data cycles notes 1st 2nd 3rd 4th n th a d a d a d a d a d lock register commands enter lock register command set (40h) x8 aaa aa 555 55 aaa 40 3 x16 555 aa 2aa 55 555 program lock register (a0h) x8 x a0 x data 5 x16 read lock register x8 x data 4, 5, 6 x16 password protection commands enter password protection command set (60h) x8 aaa aa 555 55 aaa 60 3 x16 555 aa 2aa 55 555 program password (a0h) x8 x a0 pwan pwdn 7 x16 read password x8 00 pwd0 01 pwd1 02 pwd2 03 pwd3 07 pwd7 4, 6, 8, 9 x16 00 pwd0 01 pwd1 02 pwd2 03 pwd3 unlock password (25h/ 03h) x8 00 25 00 03 00 pwd0 01 pwd1 00 29 8, 10 x16 nonvolatile protection commands enter nonvolatile protection command set (c0h) x8 aaa aa 555 55 aaa c0 3 x16 555 aa 2aa 55 555 program nonvolatile protection bit (a0h) x8 x a0 bad 00 11 x16 read nonvolatile protection bit status x8 bad read(0) 4, 6, 11 x16 clear all nonvolatile protection bits (80/30h) x8 x 80 00 30 12 x16 nonvolatile protection bit lock bit commands enter nonvolatile protection bit lock bit command set (50h) x8 aaa aa 555 55 aaa 50 3 x16 555 aa 2aa 55 555 program nonvolatile protection bit lock bit (a0h) x8 x a0 x 00 11 x16 32mb, 64mb, 128mb: 3v embedded parallel nor flash block protection command definitions C address-data cycles pdf: 09005aef84dc44a7 m29ew_32mb-128mb.pdf - rev. b 11/12 en 47 micron technology, inc. reserves the right to change products or specifications without notice. ? 2012 micron technology, inc. all rights reserved.
table 20: block protection command definitions C address-data cycles, 8-bit and 16-bit (continued) notes 1 and 2 apply to entire table command and code/subcode bus size address and data cycles notes 1st 2nd 3rd 4th n th a d a d a d a d a d read nonvolatile protection bit lock bit status x8 x read(0) 4, 6, 11 x16 volatile protection commands enter volatile protection command set (e0h) x8 aaa aa 555 55 aaa e0 3 x16 555 aa 2aa 55 555 program volatile protection bit (a0h) x8 x a0 bad 00 11 x16 read volatile protection bit status x8 bad read(0) 4, 6 x16 clear volatile protection bit (a0h) x8 x a0 bad 01 11 x16 extended memory block commands enter extended memory block (88h) x8 aaa aa 555 55 aaa 88 3 x16 555 aa 2aa 55 555 exit extended memory block (90/00h) x8 aaa aa 555 55 aaa 90 x 00 x16 555 aa 2aa 55 555 exit protection commands exit protection command set (90/00h) x8 x 90 x 00 3 x16 notes: 1. key: a = address and d = data; x = "dont care;" bad = any address in the block; pwdn = password bytes 0 to 7; pwan = password address, n = 0 to 7; gray = not applicable. all values in the table are hexadecimal. 2. dq[15:8] are "dont care" during unlock and command cycles. a[max:16] are "dont care" during unlock and command cycles, unless an address is required. 3. the enter command sequence must be issued prior to any operation. it disables read and write operations from and to block 0. read and write operations from and to any other block are allowed. also, when an enter command set command is issued, an exit protection command set command must be issued to return the device to read mode. 4. read register/password commands have no command code; ce# and oe# are driven low and data is read according to a specified address. 5. data = lock register content. 6. all address cycles shown for this command are read cycles. 7. only one portion of the password can be programmed or read by each program pass- word command. 8. each portion of the password can be entered or read in any order as long as the entire 64-bit password is entered or read. 32mb, 64mb, 128mb: 3v embedded parallel nor flash block protection command definitions C address-data cycles pdf: 09005aef84dc44a7 m29ew_32mb-128mb.pdf - rev. b 11/12 en 48 micron technology, inc. reserves the right to change products or specifications without notice. ? 2012 micron technology, inc. all rights reserved.
9. for the x8 read password command, the n th (and final) address cycle equals the 8th address cycle. from the 5th to the 8th address cycle, the values for each address and da- ta pair continue the pattern shown in the table as follows: for x8, address and data = 04 and pwd4; 05 and pwd5; 06 and pwd6; 07 and pwd7. 10. for the x8 unlock password command, the n th (and final) address cycle equals the 11th address cycle. from the 5th to the 10th address cycle, the values for each address and data pair continue the pattern shown in the table as follows: address and data = 02 and pwd2; 03 and pwd3; 04 and pwd4; 05 and pwd5; 06 and pwd6; 07 and pwd7. for the x16 unlock password command, the n th (and final) address cycle equals the 7th address cycle. for the 5th and 6th address cycles, the values for the address and data pair continue the pattern shown in the table as follows: address and data = 02 and pwd2; 03 and pwd3. 11. both nonvolatile and volatile protection bit settings are as follows: protected state = 00; unprotected state= 01. 12. the clear all nonvolatile protection bits command programs all nonvolatile pro- tection bits before erasure. this prevents over-erasure of previously cleared nonvolatile protection bits. 32mb, 64mb, 128mb: 3v embedded parallel nor flash block protection command definitions C address-data cycles pdf: 09005aef84dc44a7 m29ew_32mb-128mb.pdf - rev. b 11/12 en 49 micron technology, inc. reserves the right to change products or specifications without notice. ? 2012 micron technology, inc. all rights reserved.
protection operations blocks can be protected individually against accidental program, erase, or read op- erations on both 8-bit and 16-bit configurations. the block protection scheme is shown in the software protection scheme figure. memory block and extended memory block protection is configured through the lock register (see lock register section). lock register commands after the enter lock register command set (40h) command has been issued, all bus read or program operations can be issued to the lock register. the program lock register (a0h) command allows the lock register to be config- ured. the programmed data can then be checked with a read lock register com- mand by driving ce# and oe# low with the appropriate address data on the address bus. password protection commands after the enter password protection command set (60h) command has been issued, the commands related to password protection mode can be issued to the device. the program password (a0h) command is used to program the 64-bit password used in the password protection mode. to program the 64-bit password, the complete command sequence must be entered eight times at eight consecutive addresses selec- ted by a[1:0] plus dq15/a-1 in 8-bit mode, or four times at four consecutive addresses selected by a[1:0] in 16-bit mode. by default, all password bits are set to 1. the password can be checked by issuing a read password command. the read password command is used to verify the password used in password pro- tection mode. to verify the 64-bit password, the complete command sequence must be entered eight times at eight consecutive addresses selected by a[1:0] plus dq15/a-1 in 8-bit mode, or four times at four consecutive addresses selected by a[1:0] in 16-bit mode. if the password mode lock bit is programmed and the user attempts to read the password, the device will output ffh onto the i/o data bus. the unlock password (25/03h) command is used to clear the nonvolatile protec- tion bit lock bit, allowing the nonvolatile protection bits to be modified. the unlock password command must be issued, along with the correct password, and requires a 1 s delay between successive unlock password commands in order to prevent hackers from cracking the password by trying all possible 64-bit combinations. if this delay does not occur, the latest command will be ignored. approximately 1 s is required for unlocking the device after the valid 64-bit password has been provided. nonvolatile protection commands after the enter nonvolatile protection command set (c0h) command has been issued, the commands related to nonvolatile protection mode can be issued to the device. a block can be protected from program or erase by issuing a program nonvolatile protection bit (a0h) command, along with the block address. this command sets the nonvolatile protection bit to 0 for a given block. 32mb, 64mb, 128mb: 3v embedded parallel nor flash protection operations pdf: 09005aef84dc44a7 m29ew_32mb-128mb.pdf - rev. b 11/12 en 50 micron technology, inc. reserves the right to change products or specifications without notice. ? 2012 micron technology, inc. all rights reserved.
the status of a nonvolatile protection bit for a given block or group of blocks can be read by issuing a read nonvolatile modify protection bit command, along with the block address. the nonvolatile protection bits are erased simultaneously by issuing a clear all nonvolatile protection bits (80/30h) command. no specific block address is re- quired. if the nonvolatile protection bit lock bit is set to 0, the command fails. 32mb, 64mb, 128mb: 3v embedded parallel nor flash protection operations pdf: 09005aef84dc44a7 m29ew_32mb-128mb.pdf - rev. b 11/12 en 51 micron technology, inc. reserves the right to change products or specifications without notice. ? 2012 micron technology, inc. all rights reserved.
figure 12: program/erase nonvolatile protection bit algorithm no no yes yes dq6 = toggle enter nonvolatile protection command set start program nonvolatile protection bit addr = bad fail read byte twice addr = bad read byte twice addr = bad no no yes yes dq6 = toggle reset dq5 = 1 exit protection command set dq0 = 1 (erase) 0 (program) read byte twice addr = bad wait 500s pass 32mb, 64mb, 128mb: 3v embedded parallel nor flash protection operations pdf: 09005aef84dc44a7 m29ew_32mb-128mb.pdf - rev. b 11/12 en 52 micron technology, inc. reserves the right to change products or specifications without notice. ? 2012 micron technology, inc. all rights reserved.
nonvolatile protection bit lock bit commands after the enter nonvolatile protection bit lock bit command set (50h) command has been issued, the commands that allow the nonvolatile protection bit lock bit to be set can be issued to the device. the program nonvolatile protection bit lock bit (a0h) command is used to set the nonvolatile protection bit lock bit to 0, thus locking the nonvolatile protection bits and preventing them from being modified. the read nonvolatile protection bit lock bit status command is used to read the status of the nonvolatile protection bit lock bit. volatile protection commands after the enter volatile protection command set (e0h) command has been issued, commands related to the volatile protection mode can be issued to the device. the program volatile protection bit (a0h) command individually sets a vola- tile protection bit to 0 for a given block. if the nonvolatile protection bit for the same block is set, the block is locked regardless of the value of the volatile protection bit. (see the block protection status table.) the status of a volatile protection bit for a given block can be read by issuing a read volatile protection bit status command along with the block address. the clear volatile protection bit (a0h) command individually clears (sets to 1) the volatile protection bit for a given block. if the nonvolatile protection bit for the same block is set, the block is locked regardless of the value of the volatile protection bit. (see the block protection status table.) extended memory block commands the device has one extra 128-word extended memory block that can be accessed only by the enter extended memory block (88h) command. the extended memory block is 128 words (x16) or 256 bytes (x8). it is used as a security block to provide a per- manent 128-bit security identification number or to store additional information. the device can be shipped with the extended memory block prelocked permanently by mi- cron, including the 128-bit security identification number. or, the device can be ship- ped with the extended memory block unlocked, enabling customers to permanently program and lock it. (see lock register, the auto select command, and the block protection table.) table 21: extended memory block address and data address data x8 x16 micron prelocked customer lockable 000000hC00000fh 000000hC000007h secure id number determined by customer secure id number 000010hC0000ffh 000008hC00007fh protected and unavailable determined by customer after the enter extended memory block command has been issued, the device enters the extended memory block mode. all bus read or program operations are conducted on the extended memory block, and the extended memory block is ad- 32mb, 64mb, 128mb: 3v embedded parallel nor flash protection operations pdf: 09005aef84dc44a7 m29ew_32mb-128mb.pdf - rev. b 11/12 en 53 micron technology, inc. reserves the right to change products or specifications without notice. ? 2012 micron technology, inc. all rights reserved.
dressed using the addresses occupied by block 0 in the other operating modes (see the memory map table). in extended memory block mode, erase, chip erase, erase suspend, and erase resume commands are not allowed. the extended memory block cannot be erased, and each bit of the extended memory block can only be programmed once. the extended memory block is protected from further modification by programming lock register bit 0. once invoked, this protection cannot be undone. the device remains in extended memory block mode until the exit extended mem- ory block (90/00h) command is issued, which returns the device to read mode, or until power is removed from the device. after a power-up sequence or hardware reset, the device will revert to reading memory blocks in the main array. exit protection command the exit protection command set (90/00h) command is used to exit the lock register, password protection, nonvolatile protection, volatile protection, and nonvola- tile protection bit lock bit command set modes and return the device to read mode. 32mb, 64mb, 128mb: 3v embedded parallel nor flash protection operations pdf: 09005aef84dc44a7 m29ew_32mb-128mb.pdf - rev. b 11/12 en 54 micron technology, inc. reserves the right to change products or specifications without notice. ? 2012 micron technology, inc. all rights reserved.
device protection hardware protection the v pp /wp# function provides a hardware method of protecting either the highest/ lowest block or the top/bottom two blocks. when v pp /wp# is low, program and erase operations on either of these block options is ignored to provide protection. when v pp /wp# is high, the device reverts to the previous protection status for the highest/lowest block or top/bottom two blocks. program and erase operations can modify the data in either of these block options unless block protection is enabled. note: micron highly recommends driving v pp /wp# high or low. if a system needs to float the v pp /wp# pin, without a pull-up/pull-down resistor and no capacitor, then an internal pull-up resistor is enabled. table 22: v pp /wp# functions v pp /wp# settings function v il highest/lowest block or the top/bottom two blocks are protected. v ih highest/lowest block or the top/bottom two blocks are unprotected unless software pro- tection is activated. software protection four software protection modes are available: ? volatile protection ? nonvolatile protection ? password protection ? password access the device is shipped with all blocks unprotected. on first use, the device defaults to the nonvolatile protection mode but can be activated in either the nonvolatile protec- tion or password protection mode. the desired protection mode is activated by setting either the nonvolatile protection mode lock bit or the password protection mode lock bit of the lock register (see the lock register section). both bits are one-time-programmable and nonvolatile; therefore, af- ter the protection mode has been activated, it cannot be changed, and the device is set permanently to operate in the selected protection mode. it is recommended that the desired software protection mode be activated when first programming the device. for the lowest and highest blocks or for the top/bottom two blocks, a higher level of block protection can be achieved by locking the blocks using nonvolatile protection mode and holding v pp /wp# low. blocks with volatile protection and nonvolatile protection can coexist within the memo- ry array. if the user attempts to program or erase a protected block, the device ignores the command and returns to read mode. the block protection status can be read by performing a read electronic signature or by issuing an auto select command (see the block protection table). 32mb, 64mb, 128mb: 3v embedded parallel nor flash device protection pdf: 09005aef84dc44a7 m29ew_32mb-128mb.pdf - rev. b 11/12 en 55 micron technology, inc. reserves the right to change products or specifications without notice. ? 2012 micron technology, inc. all rights reserved.
refer to the block protection status table and the software protection scheme figure for details on the block protection scheme. refer to the protection operations section for a description of the command sets. volatile protection mode volatile protection enables the software application to protect blocks against inadver- tent change and can be disabled when changes are needed. volatile protection bits are unique for each block and can be individually modified. volatile protection bits control the protection scheme only for unprotected blocks whose nonvolatile protection bits are cleared to 1. issuing a program volatile protection bit or clear volatile protection bit command sets to 0 or clears to 1 the volatile protection bits and pla- ces the associated blocks in the protected (0) or unprotected (1) state, respectively. the volatile protection bit can be set or cleared as often as needed. when the device is first shipped, or after a power-up or hardware reset, the volatile pro- tection bits default to 1 (unprotected). nonvolatile protection mode a nonvolatile protection bit is assigned to each block. each of these bits can be set for protection individually by issuing a program nonvolatile protection bit com- mand. also, each device has one global volatile bit called the nonvolatile protection bit lock bit; it can be set to protect all nonvolatile protection bits at once. this global bit must be set to 0 only after all nonvolatile protection bits are configured to the desired settings. when set to 0, the nonvolatile protection bit lock bit prevents changes to the state of the nonvolatile protection bits. when cleared to 1, the nonvolatile protection bits can be set and cleared using the program nonvolatile protection bit and clear all nonvolatile protection bits commands, respectively. no software command unlocks the nonvolatile protection bit lock bit unless the device is in password protection mode; in nonvolatile protection mode, the nonvolatile protec- tion bit lock bit can be cleared only by taking the device through a hardware reset or power-up. nonvolatile protection bits cannot be cleared individually; they must be cleared all at once using a clear all nonvolatile protection bits command. they will re- main set through a hardware reset or a power-down/power-up sequence. if one of the nonvolatile protection bits needs to be cleared (unprotected), additional steps are required: first, the nonvolatile protection bit lock bit must be cleared to 1, us- ing either a power-cycle or hardware reset. then, the nonvolatile protection bits can be changed to reflect the desired settings. finally, the nonvolatile protection bit lock bit must be set to 0 to lock the nonvolatile protection bits. the device now will operate nor- mally. to achieve the best protection, the program nonvolatile protection lock bit command should be executed early in the boot code, and the boot code should be pro- tected by holding v pp /wp# low. nonvolatile protection bits and volatile protection bits have the same function when v pp /wp# is high or when v pp /wp# is at the voltage for program acceleration (v pph ). 32mb, 64mb, 128mb: 3v embedded parallel nor flash device protection pdf: 09005aef84dc44a7 m29ew_32mb-128mb.pdf - rev. b 11/12 en 56 micron technology, inc. reserves the right to change products or specifications without notice. ? 2012 micron technology, inc. all rights reserved.
password protection mode the password protection mode provides a higher level of security than the nonvolatile protection mode by requiring a 64-bit password to unlock the nonvolatile protection bit lock bit. in addition to this password requirement, the nonvolatile protection bit lock bit is set to 0 after power-up and reset to maintain the device in password protection mode. executing the unlock password command by entering the correct password clears the nonvolatile protection bit lock bit, enabling the block nonvolatile protection bits to be modified. if the password provided is incorrect, the nonvolatile protection bit lock bit remains locked, and the state of the nonvolatile protection bits cannot be modified. to place the device in password protection mode, the following two steps are required: first, before activating the password protection mode, a 64-bit password must be set and the setting verified. password verification is allowed only before the password pro- tection mode is activated. next, password protection mode is activated by program- ming the password protection mode lock bit to 0. this operation is irreversible. after the bit is programmed, it cannot be erased, the device remains permanently in password protection mode, and the 64-bit password can be neither retrieved nor reprogrammed. in addition, all commands to the address where the password is stored are disabled. note: there is no means to verify the password after password protection mode is ena- bled. if the password is lost after enabling the password protection mode, there is no way to clear the nonvolatile protection bit lock bit. password access password access is a security enhancement that protects information stored in the main array blocks by preventing content alteration or reads until a valid 64-bit password is received. password access may be combined with nonvolatile and/or volatile protection to create a multi-tiered solution. contact your micron sales representative for further details. figure 13: software protection scheme 1 = unprotected (default) 0 = protected 1 = unprotected 0 = protected (default setting depends on the product order option) volatile protection bit nonvolatile protection bit 1 = unlocked (default, after power-up or hardware reset) 0 = locked nonvolatile protection bit lock bit (volatile) nonvolatile protection mode password protection mode volatile protection nonvolatile protection array block 32mb, 64mb, 128mb: 3v embedded parallel nor flash device protection pdf: 09005aef84dc44a7 m29ew_32mb-128mb.pdf - rev. b 11/12 en 57 micron technology, inc. reserves the right to change products or specifications without notice. ? 2012 micron technology, inc. all rights reserved.
notes: 1. volatile protection bits are programmed and cleared individually. nonvolatile protection bits are programmed individually and cleared collectively. 2. once programmed to 0, the nonvolatile protection bit lock bit can be reset to 1 only by taking the device through a power-up or hardware reset. 32mb, 64mb, 128mb: 3v embedded parallel nor flash device protection pdf: 09005aef84dc44a7 m29ew_32mb-128mb.pdf - rev. b 11/12 en 58 micron technology, inc. reserves the right to change products or specifications without notice. ? 2012 micron technology, inc. all rights reserved.
common flash interface the common flash interface (cfi) is a jedec-approved, standardized data structure that can be read from the flash memory device. it allows a system's software to query the device to determine various electrical and timing parameters, density information, and functions supported by the memory. the system can interface easily with the de- vice, enabling the software to upgrade itself when necessary. when the read cfi query command is issued, the device enters cfi query mode and the data structure is read from memory. the following tables show the addresses (a-1, a[7:0]) used to retrieve the data. the query data is always presented on the lowest order data outputs (dq[7:0]), and the other data outputs (dq[15:8]) are set to 0. table 23: query structure overview note 1 applies to the entire table address subsection name description x16 x8 10h 20h cfi query identification string command set id and algorithm data offset 1bh 36h system interface information device timing and voltage information 27h 4eh device geometry definition flash device layout 40h 80h primary algorithm-specific extended query table additional information specific to the primary al- gorithm (optional) note: 1. query data are always presented on the lowest order data outputs (dq[7:0]). dq[15:8] are set to 0. table 24: cfi query identification string note 1 applies to the entire table address data description value x16 x8 10h 20h 0051h query unique ascii string "qry" "q" 11h 22h 0052h "r" 12h 24h 0059h "y" 13h 14h 26h 28h 0002h 0000h primary algorithm command set and control interface id code 16-bit id code defining a specific algorithm C 15h 16h 2ah 2ch 0040h 0000h address for primary algorithm extended query table (see the primary algo- rithm-specific extended query table) p = 40h 17h 18h 2eh 30h 0000h 0000h alternate vendor command set and control interface id code second ven- dor-specified algorithm supported C 19h 1ah 32h 34h 0000h 0000h address for alternate algorithm extended query table C note: 1. query data are always presented on the lowest order data outputs (dq[7:0]). dq[15:8] are set to 0. 32mb, 64mb, 128mb: 3v embedded parallel nor flash common flash interface pdf: 09005aef84dc44a7 m29ew_32mb-128mb.pdf - rev. b 11/12 en 59 micron technology, inc. reserves the right to change products or specifications without notice. ? 2012 micron technology, inc. all rights reserved.
table 25: cfi query system interface information note 1 applies to the entire table address data description value x16 x8 1bh 36h 0027h v cc logic supply minimum program/erase voltage bits[7:4] bcd value in volts bits[3:0] bcd value in 100mv 2.7v 1ch 38h 0036h v cc logic supply maximum program/erase voltage bits[7:4] bcd value in volts bits[3:0] bcd value in 100mv 3.6v 1dh 3ah 00b5h v pph (programming) supply minimum program/erase voltage bits[7:4] hex value in volts bits[3:0] bcd value in 100mv 11.5v 1eh 3ch 00c5h v pph (programming) supply maximum program/erase voltage bits[7:4] hex value in volts bits[3:0] bcd value in 100mv 12.5v 1fh 3eh 0004h typical timeout for single byte/word program = 2 n s 16s 20h 40h 0009h typical timeout for maximum size buffer program = 2 n s 512s 21h 42h 0009h typical timeout per individual block erase = 2 n ms 0.5s 22h 44h 000fh typical timeout for full chip erase = 2 n ms 32mb: 33s 0010h 64mb: 66s 0011h 128mb: 131s 23h 46h 0004h maximum timeout for byte/word program = 2 n times typical 256s 24h 48h 0002h maximum timeout for buffer program = 2 n times typical 2048s 25h 4ah 0003h maximum timeout per individual block erase = 2 n times typical 4s 26h 4ch 0002h maximum timeout for chip erase = 2 n times typical 32mb: 131s 0002h 64mb: 262s 0002h 128mb: 524s note: 1. the values in this table are valid for all packages. table 26: device geometry definition address data description value x16 x8 27h 4eh 0016h device size = 2 n in number of bytes 4mb 0017h 8mb 0018h 16mb 28h 29h 50h 52h 0002h 0000h flash device interface code description x8, x16 asynchro- nous 2ah 2bh 54h 56h 0008h 1 0000h maximum number of bytes in multi-byte program or page = 2 n 256 32mb, 64mb, 128mb: 3v embedded parallel nor flash common flash interface pdf: 09005aef84dc44a7 m29ew_32mb-128mb.pdf - rev. b 11/12 en 60 micron technology, inc. reserves the right to change products or specifications without notice. ? 2012 micron technology, inc. all rights reserved.
table 26: device geometry definition (continued) address data description value x16 x8 2ch 58h (see table below) number of erase block regions. it specifies the number of regions containing contiguous erase blocks of the same size. 01h = uniform device 02h = boot device C 2dh 2eh 2fh 30h 5ah 5ch 5eh 60h (see table below) erase block region 1 information bits[15:0] = y, y + 1 = number of identical-size erase blocks bits[31:16] = z, block size in region 1 is z x 256 bytes C 31h 32h 33h 34h 62h 64h 66h 68h (see table below) erase block region 2 information bits[15:0] = y, y + 1 = number of identical-size erase blocks bits[31:16] = z, block size in region 1 is z x 256 bytes C 35h 36h 37h 38h 6ah 6ch 6eh 70h 0000h 0000h 0000h 0000h erase block region 3 information 0 39h 3ah 3bh 3ch 72h 74h 76h 78h 0000h 0000h 0000h 0000h erase block region 4 information 0 note: 1. the value at 2ah in the cfi region is set to 08h (256 bytes) due to compatibility issues. the maximum 256-word program buffer can be used to optimize system program per- formance. table 27: erase block region information address 32mb 64mb 128mb top bottom uniform top bottom uniform uniform 2ch 02h 02h 01h 02h 02h 01h 01h 2dh 07h 07h 3fh 07h 07h 7fh 7fh 2eh 00h 00h 00h 00h 00h 00h 00h 2fh 20h 20h 00h 20h 20h 00h 00h 30h 00h 00h 01h 00h 00h 01h 02h 31h 3eh 3eh 00h 7eh 7eh 00h 00h 32h 00h 00h 00h 00h 00h 00h 00h 33h 00h 00h 00h 00h 00h 00h 00h 34h 01h 01h 00h 01h 01h 00h 00h 32mb, 64mb, 128mb: 3v embedded parallel nor flash common flash interface pdf: 09005aef84dc44a7 m29ew_32mb-128mb.pdf - rev. b 11/12 en 61 micron technology, inc. reserves the right to change products or specifications without notice. ? 2012 micron technology, inc. all rights reserved.
table 28: primary algorithm-specific extended query table note 1 applies to the entire table address data description value x16 x8 40h 80h 0050h primary algorithm extended query table unique ascii string pri "p" 41h 82h 0052h "r" 42h 84h 0049h "i" 43h 86h 0031h major version number, ascii "1" 44h 88h 0033h minor version number, ascii "3" 45h 8ah 0018h address sensitive unlock (bits[1:0]): 00 = required 01 = not required silicon revision number (bits[7:2]) required 46h 8ch 0002h erase suspend: 00 = not supported 01 = read only 02 = read and write 2 47h 8eh 0001h block protection: 00 = not supported x = number of blocks per group 1 48h 90h 0000h temporary block unprotect: 00 = not supported 01 = supported not supported 49h 92h 0008h block protect/unprotect: 08 = m29ewh/m29ewl 8 4ah 94h 0000h simultaneous operations: not supported n/a 4bh 96h 0000h burst mode: 00 = not supported 01 = supported not supported 4ch 98h 0002h page mode: 00 = not supported 01 = 8-word page 02 = 8-word page 03 = 16-word page 8-word page 4dh 9ah 00b5h v pph supply minimum program/erase voltage: bits[7:4] hex value in volts bits[3:0] bcd value in 100mv 11.5v 4eh 9ch 00c5h v pph supply maximum program/erase voltage: bits[7:4] hex value in volts bits[3:0] bcd value in 100mv 12.5v 32mb, 64mb, 128mb: 3v embedded parallel nor flash common flash interface pdf: 09005aef84dc44a7 m29ew_32mb-128mb.pdf - rev. b 11/12 en 62 micron technology, inc. reserves the right to change products or specifications without notice. ? 2012 micron technology, inc. all rights reserved.
table 28: primary algorithm-specific extended query table (continued) note 1 applies to the entire table address data description value x16 x8 4fh 9eh 00xxh top/bottom boot block flag: xx = 02h: bottom boot device, hw protection for bottom two blocks xx = 03h: top boot device, hw protection for top two blocks xx = 04h: uniform device, hw protection for lowest block xx = 05h: uniform device, hw protection for highest block device type (bot- tom boot, top boot, uniform) 50h a0h 0001h program suspend: 00 = not supported 01 = supported supported note: 1. the values in this table are valid for both packages. 32mb, 64mb, 128mb: 3v embedded parallel nor flash common flash interface pdf: 09005aef84dc44a7 m29ew_32mb-128mb.pdf - rev. b 11/12 en 63 micron technology, inc. reserves the right to change products or specifications without notice. ? 2012 micron technology, inc. all rights reserved.
power-up and reset characteristics table 29: power-up specifications parameter symbol min unit notes legacy jedec v cc high to v ccq high C t vchvcqh 0 s 1 v cc high to rising edge of rst# t vcs t vchph 60 s 2 v ccq high to rising edge of rst# t vios t vcqhph 0 s 2 rst# high to chip enable low t rh t phel 50 ns rst# high to write enable low C t phwl 150 ns notes: 1. v cc and v ccq ramps must be synchronized during power-up. 2. if rst# is not stable for t vcs or t vios, the device will not allow any read or write oper- ations, and a hardware reset is required. figure 14: power-up timing t rh t vios t vcs t phwl t vchvcqh v ccq v cc ce# rst# we# 32mb, 64mb, 128mb: 3v embedded parallel nor flash power-up and reset characteristics pdf: 09005aef84dc44a7 m29ew_32mb-128mb.pdf - rev. b 11/12 en 64 micron technology, inc. reserves the right to change products or specifications without notice. ? 2012 micron technology, inc. all rights reserved.
table 30: reset ac specifications condition/parameter symbol min max unit notes legacy jedec rst# low to read mode during program or erase t ready t plrh C 25 s 1 rst# pulse width t rp t plph 100 C ns rst# high to ce# low, oe# low t rh t phel, t phgl 50 C ns 1 rst# low to standby mode during read mode t rpd C 10 C s rst# low to standby mode during program or erase 50 C s ry/by# high to ce# low, oe# low t rb t rhel, t rhgl 0 C ns 1 note: 1. sampled only; not 100% tested. figure 15: reset ac timing C no program/erase operation in progress t rh ry/by# ce#, oe# rst# t rp figure 16: reset ac timing during program/erase operation t rb ry/by# ce#, oe# rst# t rp t rh t ready 32mb, 64mb, 128mb: 3v embedded parallel nor flash power-up and reset characteristics pdf: 09005aef84dc44a7 m29ew_32mb-128mb.pdf - rev. b 11/12 en 65 micron technology, inc. reserves the right to change products or specifications without notice. ? 2012 micron technology, inc. all rights reserved.
absolute ratings and operating conditions stresses greater than those listed may cause permanent damage to the device. this is a stress rating only, and functional operation of the device at these or any other condi- tions outside those indicated in the operational sections of this specification is not im- plied. exposure to absolute maximum rating conditions for extended periods may ad- versely affect reliability. table 31: absolute maximum/minimum ratings parameter symbol min max units notes temperature under bias t bias C40 85 c storage temperature t stg C65 125 c input/output voltage v io C0.6 v cc + 0.6 v 1, 2 supply voltage v cc C2 5.6 v 1, 2 input/output supply voltage v ccq C2 5.6 v 1, 2 program voltage v pph C2 14.5 v 1, 2, 3 notes: 1. during signal transitions, minimum voltage may undershoot to ?2v during periods less than 20ns. 2. during signal transitions, maximum voltage may overshoot to v cc + 2v for periods less than 20ns. 3. v pph must not remain at 12v for more than 80 hours cumulative. table 32: operating conditions parameter symbol min max unit supply voltage v cc 2.7 3.6 v input/output supply voltage (v ccq v cc ) v ccq 1.65 3.6 v program voltage v pp C0.6 12.5 v ambient operating temperature t a C40 85 c load capacitance c l 30 pf input rise and fall times C C 2.5 ns input pulse voltages C 0 to v ccq v input and output timing reference voltages C v ccq /2 v 32mb, 64mb, 128mb: 3v embedded parallel nor flash absolute ratings and operating conditions pdf: 09005aef84dc44a7 m29ew_32mb-128mb.pdf - rev. b 11/12 en 66 micron technology, inc. reserves the right to change products or specifications without notice. ? 2012 micron technology, inc. all rights reserved.
figure 17: ac measurement load circuit c l v ccq 25k device under test 0.1f v cc 0.1f v pp 25k note: 1. c l includes jig capacitance. figure 18: ac measurement i/o waveform v ccq 0v v ccq /2 table 33: input/output capacitance parameter symbol test condition min max unit input capacitance c in v in = 0v 2 7 pf output capacitance c out v out = 0v 2 5 pf 32mb, 64mb, 128mb: 3v embedded parallel nor flash absolute ratings and operating conditions pdf: 09005aef84dc44a7 m29ew_32mb-128mb.pdf - rev. b 11/12 en 67 micron technology, inc. reserves the right to change products or specifications without notice. ? 2012 micron technology, inc. all rights reserved.
dc characteristics table 34: dc current characteristics parameter symbol conditions min typ max unit notes input leakage current i li 0v v in v cc C C 1 a 1 output leakage current i lo 0v v out v cc C C 1 a v cc read current random read i cc1 ce# = v il , oe# = v ih , f = 5 mhz C 20 25 ma page read ce# = v il , oe# = v ih , f = 13 mhz C 12 16 ma v cc standby current 128mb i cc2 ce# = v ccq 0.2v, rst# = v ccq 0.2v C 50 120 a 64mb C 35 120 a 32mb C 35 120 a v cc program/erase/blank check current i cc3 program/ erase controller active v pp /wp# = v il or v ih C 35 50 ma 2 v pp /wp# = v pph C 26 33 ma v pp current read i pp1 v pp /wp# v cc C 2 15 a standby C 0.2 5 a reset i pp2 rst# = v ss 0.2v C 0.2 5 a program operation ongoing i pp3 v pp /wp# = 12v 5% C 5 10 ma v pp /wp# = v cc C 0.05 0.10 ma erase operation ongoing i pp4 v pp /wp# = 12v 5% C 5 10 ma v pp /wp# = v cc C 0.05 0.10 ma notes: 1. the maximum input leakage current is 5a on the v pp /wp# pin. 2. sampled only; not 100% tested. 32mb, 64mb, 128mb: 3v embedded parallel nor flash dc characteristics pdf: 09005aef84dc44a7 m29ew_32mb-128mb.pdf - rev. b 11/12 en 68 micron technology, inc. reserves the right to change products or specifications without notice. ? 2012 micron technology, inc. all rights reserved.
table 35: dc voltage characteristics parameter symbol conditions min typ max unit notes input low voltage v il v cc 2.7v C0.5 C 0.8 v input high voltage v ih v cc 2.7v v ccq C0.4 C v ccq +0.5 v 1 output low voltage v ol i ol = 100a, v cc = v cc,min , v ccq = v ccq,min C C 0.2 v output high voltage v oh i oh = 100a, v cc = v cc,min , v ccq = v ccq,min v ccq - 0.2 C C v voltage for v pp /wp# program acceleration v pph C 11.5 C 12.5 v v pp logic level v ppl 2.7 C 3.6 v program/erase lockout supply voltage v lko C 2.3 C C v 2 notes: 1. if v ccq range is 2.7v~3.6v, v ih min is 2v. 2. sampled only; not 100% tested. 32mb, 64mb, 128mb: 3v embedded parallel nor flash dc characteristics pdf: 09005aef84dc44a7 m29ew_32mb-128mb.pdf - rev. b 11/12 en 69 micron technology, inc. reserves the right to change products or specifications without notice. ? 2012 micron technology, inc. all rights reserved.
read ac characteristics table 36: read ac characteristics parameter symbol condition package min max unit notes legacy jedec address valid to next address valid t rc t avav ce# = v il , oe# = v il bga 60 C ns tsop 70 C ns address valid to output valid t acc t avqv ce# = v il , oe# = v il bga C 60 ns tsop C 70 ns address valid to output valid (page) t page t avqv1 ce# = v il , oe# = v il bga C 25 ns tsop C 25 ns ce# low to output transition t lz t elqx oe# = v il bga 0 C ns 1 tsop 0 C ns 1 ce# low to output valid t e t elqv oe# = v il bga C 60 ns tsop C 70 ns oe# low to output transition t olz t glqx ce# = v il bga 0 C ns 1 tsop 0 C ns 1 oe# low to output valid t oe t glqv ce# = v il bga C 25 ns tsop C 25 ns ce# high to output high-z t hz t ehqz oe# = v il bga C 20 ns 1 tsop C 20 ns 1 oe# high to output high-z t df t ghqz ce# = v il bga C 15 ns 1 tsop C 15 ns 1 ce#, oe#, or address transition to output transition t oh t ehqx, t ghqx, t axqx C bga 0 C ns tsop 0 C ns ce# to byte# low t elfl t elbl C bga C 10 ns tsop C 10 ns ce# to byte# high t elfh t elbh C bga C 10 ns tsop C 10 ns byte# low to output valid t flqv t blqv C bga C 1 s tsop C 1 s byte# high to output valid t fhqv t bhqv C bga C 1 s tsop C 1 s byte# low to output in high-z t flqz t blqz C bga C 1 s tsop C 1 s note: 1. sampled only; not 100% tested. 32mb, 64mb, 128mb: 3v embedded parallel nor flash read ac characteristics pdf: 09005aef84dc44a7 m29ew_32mb-128mb.pdf - rev. b 11/12 en 70 micron technology, inc. reserves the right to change products or specifications without notice. ? 2012 micron technology, inc. all rights reserved.
figure 19: random read ac timing (8-bit mode) valid valid t acc t rc t oh t e t elfl t flqz t lz t oh t hz t olz t oh t oe t df a[max:0]/a-1 ce# oe# dq[7:0] byte# figure 20: random read ac timing (16-bit mode) valid valid t acc t rc t oh t e t elfh t lz t oh t hz t olz t oh t oe t df a[max:0] ce# oe# dq[15:0] byte# 32mb, 64mb, 128mb: 3v embedded parallel nor flash read ac characteristics pdf: 09005aef84dc44a7 m29ew_32mb-128mb.pdf - rev. b 11/12 en 71 micron technology, inc. reserves the right to change products or specifications without notice. ? 2012 micron technology, inc. all rights reserved.
figure 21: byte# transition read ac timing data-out data-out valid valid t acc t oh t fhqv t blqx high-z a[max:0] aC1 byte# dq[7:0] dq[15:8] figure 22: page read ac timing (16-bit mode) valid valid valid valid valid valid valid valid t acc t e t page t oh t hz t oh t oe t df a[max:4] a[3:0] ce# oe# dq[15:0] valid valid valid valid valid valid valid note: 1. page size is 8 words (16 bytes) and is addressed by address inputs a[2:0] in x16 bus mode and a[2:0] plus dq15/a?1 in x8 bus mode. 32mb, 64mb, 128mb: 3v embedded parallel nor flash read ac characteristics pdf: 09005aef84dc44a7 m29ew_32mb-128mb.pdf - rev. b 11/12 en 72 micron technology, inc. reserves the right to change products or specifications without notice. ? 2012 micron technology, inc. all rights reserved.
write ac characteristics table 37: we#-controlled write ac characteristics parameter symbol package min typ max unit notes legacy jedec address valid to next address valid t wc t avav bga 60 C C ns tsop 70 C C ns ce# low to we# low t cs t elwl bga 0 C C ns tsop 0 C C ns we# low to we# high t wp t wlwh bga 35 C C ns tsop 35 C C ns input valid to we# high t ds t dvwh bga 30 C C ns tsop 30 C C ns we# high to input transition t dh t whdx bga 0 C C ns tsop 0 C C ns we# high to ce# high t ch t wheh bga 0 C C ns tsop 0 C C ns we# high to we# low t wph t whwl bga 20 C C ns tsop 20 C C ns address valid to we# low t as t avwl bga 0 C C ns tsop 0 C C ns we# low to address transition t ah t wlax bga 45 C C ns tsop 45 C C ns oe# high to we# low C t ghwl bga 0 C C ns tsop 0 C C ns we# high to oe# low t oeh t whgl bga 0 C C ns tsop 0 C C ns program/erase valid to ry/by# low t busy t whrl bga C C 90 ns 1 tsop C C 90 ns 1 v cc high to ce# low t vcs t vchel bga 60 C C s tsop 60 C C s note: 1. sampled only; not 100% tested. 32mb, 64mb, 128mb: 3v embedded parallel nor flash write ac characteristics pdf: 09005aef84dc44a7 m29ew_32mb-128mb.pdf - rev. b 11/12 en 73 micron technology, inc. reserves the right to change products or specifications without notice. ? 2012 micron technology, inc. all rights reserved.
figure 23: we#-controlled program ac timing (8-bit mode) aaah pa pa 3rd cycle 4th cycle read cycle data polling t wc t wc t as t wp t ds t whwh1 t df t wph t ah t e t cs t ghwl t oe t dh t oh t ch a[max:0]/a-1 ce# oe# we# dq[7:0] aoh pd dq7# d out d out notes: 1. only the third and fourth cycles of the program command are represented. the pro- gram command is followed by checking of the status register data polling bit and by a read operation that outputs the data (d out ) programmed by the previous program command. 2. pa is the address of the memory location to be programmed. pd is the data to be pro- grammed. 3. dq7 is the complement of the data bit being programmed to dq7 (see data polling bit [dq7]). 4. see the following tables for timing details: read ac characteristics, we#-controlled write ac characteristics, and ce#-controlled write ac characteristics. 32mb, 64mb, 128mb: 3v embedded parallel nor flash write ac characteristics pdf: 09005aef84dc44a7 m29ew_32mb-128mb.pdf - rev. b 11/12 en 74 micron technology, inc. reserves the right to change products or specifications without notice. ? 2012 micron technology, inc. all rights reserved.
figure 24: we#-controlled program ac timing (16-bit mode) 555h pa pa 3rd cycle 4th cycle read cycle data polling t wc t wc t as t wp t ds t df t whwh1 t wph t ah t e t cs t ghwl t oe t dh t oh t ch a[max:0] ce# oe# we# dq[15:0] aoh pd dq7# d out d out notes: 1. only the third and fourth cycles of the program command are represented. the pro- gram command is followed by checking of the status register data polling bit and by a read operation that outputs the data (d out ) programmed by the previous program command. 2. pa is the address of the memory location to be programmed. pd is the data to be pro- grammed. 3. dq7 is the complement of the data bit being programmed to dq7 (see data polling bit [dq7]). 4. see the following tables for timing details: read ac characteristics, we#-controlled write ac characteristics, and ce#-controlled write ac characteristics. 32mb, 64mb, 128mb: 3v embedded parallel nor flash write ac characteristics pdf: 09005aef84dc44a7 m29ew_32mb-128mb.pdf - rev. b 11/12 en 75 micron technology, inc. reserves the right to change products or specifications without notice. ? 2012 micron technology, inc. all rights reserved.
table 38: ce#-controlled write ac characteristics parameter symbol package min typ max unit legacy jedec address valid to next address valid t wc t avav bga 60 C C ns tsop 70 C C ns we# low to ce# low t ws t wlel bga 0 C C ns tsop 0 C C ns ce# low to ce# high t cp t eleh bga 35 C C ns tsop 35 C C ns input valid to ce# high t ds t dveh bga 30 C C ns tsop 30 C C ns ce# high to input transition t dh t ehdx bga 0 C C ns tsop 0 C C ns ce# high to we# high t wh t ehwh bga 0 C C ns tsop 0 C C ns ce# high to ce# low t cph t ehel bga 20 C C ns tsop 20 C C ns address valid to ce# low t as t avel bga 0 C C ns tsop 0 C C ns ce# low to address transition t ah t elax bga 45 C C ns tsop 45 C C ns oe# high to ce# low C t ghel bga 0 C C ns tsop 0 C C ns 32mb, 64mb, 128mb: 3v embedded parallel nor flash write ac characteristics pdf: 09005aef84dc44a7 m29ew_32mb-128mb.pdf - rev. b 11/12 en 76 micron technology, inc. reserves the right to change products or specifications without notice. ? 2012 micron technology, inc. all rights reserved.
figure 25: ce#-controlled program ac timing (8-bit mode) aaah pa pa 3rd cycle 4th cycle data polling t wc t as t cp t ds t whwh1 t cph t ah t ws t ghel t dh t wh a[max:0]/a-1 we# oe# ce# dq[7:0] aoh pd dq7# d out notes: 1. only the third and fourth cycles of the program command are represented. the pro- gram command is followed by checking of the status register data polling bit. 2. pa is the address of the memory location to be programmed. pd is the data to be pro- grammed. 3. dq7 is the complement of the data bit being programmed to dq7 (see data polling bit [dq7]). 4. see the following tables for timing details: read ac characteristics, we#-controlled write ac characteristics, and ce#-controlled write ac characteristics. 32mb, 64mb, 128mb: 3v embedded parallel nor flash write ac characteristics pdf: 09005aef84dc44a7 m29ew_32mb-128mb.pdf - rev. b 11/12 en 77 micron technology, inc. reserves the right to change products or specifications without notice. ? 2012 micron technology, inc. all rights reserved.
figure 26: ce#-controlled program ac timing (16-bit mode) 555h pa pa 3rd cycle 4th cycle data polling t wc t as t cp t ds t whwh1 t cph t ah t ws t ghel t dh t wh a[max:0] we# oe# ce# dq[15:0] aoh pd dq7# d out notes: 1. only the third and fourth cycles of the program command are represented. the pro- gram command is followed by checking of the status register data polling bit. 2. pa is the address of the memory location to be programmed. pd is the data to be pro- grammed. 3. dq7 is the complement of the data bit being programmed to dq7 (see data polling bit [dq7]). 4. see the following tables for timing details: read ac characteristics, we#-controlled write ac characteristics, and ce#-controlled write ac characteristics. 32mb, 64mb, 128mb: 3v embedded parallel nor flash write ac characteristics pdf: 09005aef84dc44a7 m29ew_32mb-128mb.pdf - rev. b 11/12 en 78 micron technology, inc. reserves the right to change products or specifications without notice. ? 2012 micron technology, inc. all rights reserved.
figure 27: chip/block erase ac timing (8-bit mode) aaah t wc t as t wp t ds t wph t ah t cs t ghwl t dh t ch a[max:0]/ aC1 ce# oe# we# dq[7:0] aah 555h aaah aaah bah 1 555h aaah 55h 55h aah 80h 10h/ 30h notes: 1. for a chip erase command, the address is 555h, and the data is 10h; for a block erase command, the address is bad, and the data is 30h. 2. bad is the block address. 3. see the following tables for timing details: read ac characteristics, we#-controlled write ac characteristics, and ce#-controlled write ac characteristics. 32mb, 64mb, 128mb: 3v embedded parallel nor flash write ac characteristics pdf: 09005aef84dc44a7 m29ew_32mb-128mb.pdf - rev. b 11/12 en 79 micron technology, inc. reserves the right to change products or specifications without notice. ? 2012 micron technology, inc. all rights reserved.
accelerated program, data polling/toggle ac characteristics table 39: accelerated program and data polling/data toggle ac characteristics parameter symbol min max unit legacy jedec v pp /wp# rising or falling time C t vhvpp 250 C ns valid v hh on v pp /wp# to we# high C t vhhwh 50 C ns address setup time to oe# low during toggle bit polling t aso t axgl 15 C ns address hold time from oe# during toggle bit polling t aht t ghax, t ehax 0 C ns ce# high during toggle bit polling t eph t ehel2 20 C ns output hold time during data and toggle bit polling t oeh t whgl2, t ghgl2 20 C ns program/erase valid to ry/by# low t busy t whrl C 90 ns note: 1. sampled only; not 100% tested. figure 28: accelerated program ac timing t vhvpp t vhvpp v pph v il or v ih v pp /wp# figure 29: data polling ac timing dq7# data dq7# valid dq7 data output flag data output flag valid dq[6:0] data t hz/ t df t e t oe t ch t busy t oeh ce# oe# we# dq[6:0] dq7 ry/by# 32mb, 64mb, 128mb: 3v embedded parallel nor flash accelerated program, data polling/toggle ac characteristics pdf: 09005aef84dc44a7 m29ew_32mb-128mb.pdf - rev. b 11/12 en 80 micron technology, inc. reserves the right to change products or specifications without notice. ? 2012 micron technology, inc. all rights reserved.
notes: 1. dq7 returns a valid data bit when the program or erase command has completed. 2. see the following tables for timing details: read ac characteristics, accelerated pro- gram and data polling/data toggle ac characteristics. figure 30: toggle/alternative toggle bit polling ac timing (8-bit mode) toggle toggle toggle data stop toggling output valid t busy t oeh t eph t oeh ce# we# oe# dq6/dq2 ry/by# t oeh t aht t aso t aht t dh t as a[max:0]/ aC1 t oe t e notes: 1. dq6 stops toggling when the program or erase command has completed. dq2 stops toggling when the chip erase or block erase command has completed. 2. see the following tables for timing details: read ac characteristics, accelerated pro- gram and data polling/data toggle ac characteristics. 32mb, 64mb, 128mb: 3v embedded parallel nor flash accelerated program, data polling/toggle ac characteristics pdf: 09005aef84dc44a7 m29ew_32mb-128mb.pdf - rev. b 11/12 en 81 micron technology, inc. reserves the right to change products or specifications without notice. ? 2012 micron technology, inc. all rights reserved.
electrical specifications C program/erase characteristics table 40: program/erase characteristics parameter buffer size byte word min typ 1, 2 max 2 unit block erase C C C C 0.5 4 s erase suspend latency C C C C 20 25 s block erase timeout C C C 50 C C s byte program single-byte program C C C C 15 175 s double-/ quadruple-/ octuple-byte program C C C C 10 200 s byte write to buffer program 32 32 C C 70 200 s 64 64 C C 85 200 s 256 256 C C 160 710 s effective write to buffer program per byte 32 1 C C 2.19 6.25 s 64 1 C C 1.33 3.125 s 256 1 C C 0.625 2.77 s word program single-word program C C C C 15 175 s word write to buffer program 16 C 16 C 70 200 s 32 C 32 C 85 200 s 128 C 128 C 160 710 s 256 C 256 C 284 1280 s full buffer program with v pph 256 C 256 C 160 800 s effective write to buffer program per word 16 C 1 C 4.375 12.5 s 32 C 1 C 2.66 6.25 s 128 C 1 C 1.25 5.55 s 256 C 1 C 1.11 5 s effective full buffer program per word with v pph 256 C 1 C 0.625 3.125 s program suspend latency C C C C 20 25 s blank check C C C C 3.2 C ms program/erase cycles (per block) C C C 100,000 C C cycles notes: 1. typical values measured at room temperature and nominal voltages. 2. sampled, but not 100% tested. 32mb, 64mb, 128mb: 3v embedded parallel nor flash electrical specifications C program/erase characteristics pdf: 09005aef84dc44a7 m29ew_32mb-128mb.pdf - rev. b 11/12 en 82 micron technology, inc. reserves the right to change products or specifications without notice. ? 2012 micron technology, inc. all rights reserved.
package dimensions figure 31: 56-pin tsop C 14mm x 20mm see detail a 0.50 typ 14.00 0.10 1.20 max 18.40 0.10 20.00 0.20 1.00 0.05 0.10 0.05 0.22 0.05 detail a 0.50 0.10 3 typ/ 5 max 0.10 0.10 min/ 0.21 max pin #1 notes: 1. all dimensions are in millimeters. 2. for the lead width value of 0.22 0.05, there is also a legacy value of 0.15 0.05. 32mb, 64mb, 128mb: 3v embedded parallel nor flash package dimensions pdf: 09005aef84dc44a7 m29ew_32mb-128mb.pdf - rev. b 11/12 en 83 micron technology, inc. reserves the right to change products or specifications without notice. ? 2012 micron technology, inc. all rights reserved.
figure 32: 48-pin tsop C 12mm x 20mm die 1 24 48 25 0.50 typ 0.10 max 0.10 min/ 0.21 max 0.60 + 0.10 + 3 o 2 o 3 o 0.22 + 0.05 0.10 + 0.05 1.20 max 1.00 + 0.05 0.80 typ 20.00 + 0.20 18.40 + 0.10 12.00 + 0.10 note: 1. all dimensions are in millimeters. 32mb, 64mb, 128mb: 3v embedded parallel nor flash package dimensions pdf: 09005aef84dc44a7 m29ew_32mb-128mb.pdf - rev. b 11/12 en 84 micron technology, inc. reserves the right to change products or specifications without notice. ? 2012 micron technology, inc. all rights reserved.
figure 33: 48-ball bga C 6mm x 8mm ball a1 5.60 typ 1.00 max 0.64 typ 0.10 max 0.20 min 1.00 typ 0.40 typ 4.00 typ 0.40 typ 1.20 typ 0.80 typ 0.80 typ 8.00 + 0.10 0.35 + 0.5 6.00 + 0.10 note: 1. all dimensions are in millimeters. 32mb, 64mb, 128mb: 3v embedded parallel nor flash package dimensions pdf: 09005aef84dc44a7 m29ew_32mb-128mb.pdf - rev. b 11/12 en 85 micron technology, inc. reserves the right to change products or specifications without notice. ? 2012 micron technology, inc. all rights reserved.
figure 34: 64-ball fortified bga C 11mm x 13mm seating plane 0.80 typ 0.10 13.00 0.10 0.60 0.05 1.00 typ 3.00 typ a b c d e f g h 7.00 typ 1.40 max ball a1 id 1.00 typ 2.00 typ 0.49 typ/ 0.40 min 11.00 0.10 7.00 typ 64x 8 7 6 5 4 3 2 1 note: 1. all dimensions are in millimeters. 32mb, 64mb, 128mb: 3v embedded parallel nor flash package dimensions pdf: 09005aef84dc44a7 m29ew_32mb-128mb.pdf - rev. b 11/12 en 86 micron technology, inc. reserves the right to change products or specifications without notice. ? 2012 micron technology, inc. all rights reserved.
revision history rev. b C 11/12 ? added text to signal descriptions to clarify v pp /wp# and vss decoupling require- ment. ? added note to dc voltage characteristics table to clarify vih spec. rev. a C 08/12 ? initial micron rebrand release 8000 s. federal way, p.o. box 6, boise, id 83707-0006, tel: 208-368-3900 www.micron.com/productsupport customer comment line: 800-932-4992 micron and the micron logo are trademarks of micron technology, inc. all other trademarks are the property of their respective owners. this data sheet contains minimum and maximum limits specified over the power supply and temperature range set forth herein. although considered final, these specifications are subject to change, as further product development and data characterization some- times occur. 32mb, 64mb, 128mb: 3v embedded parallel nor flash revision history pdf: 09005aef84dc44a7 m29ew_32mb-128mb.pdf - rev. b 11/12 en 87 micron technology, inc. reserves the right to change products or specifications without notice. ? 2012 micron technology, inc. all rights reserved.

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